Other Parts Discussed in Thread: ADC3662, ADC3663
Dear E2E Team!
we use ADC3661 in 1-wire SLVDS output bit mapper. ADC digital data output based on DCLKIN, DCLK and FCLK.
Sampling clock falling edge to DCLK rising edge (tPD ) depends on sampling clock falling edge to DCLKIN falling edge (tCDCLK)
If tCDCLK <2.5 ns the delay tPD (first rising edge of DCLK after sampling clock falling edge) amounts to 3ns+ TDCLK + tCDCLK . This delay is larger as TDCLKIN , in our case 1/64 MHz.
Because tPD > TDCLK we infer timing variation between DCLKIN and DCLK. How is the duty cycle of DCLK wrt DCLKIN? We expect fDCLK = fDCLKI !?
For implementation can we expect that serial data transition on ADC output is a result of DCLK edge event. This is very hard to understand because tCD min = 0 ns specify no delay between data and DCLK.
From my point of view a data transfer using DDR register appears uncertain without delay between data and DCLK!? Can you provide any insights of implementation for digital data acquisition?
( source: ADC3661, ADC3662, ADC3663 SBAS991B – FEBRUARY 2021 – REVISED SEPTEMBER 2022)
Best regards
Thomas
