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TVP20025I, ALC (automatic level control) register setting question.

Michael Korejwo
Prodigy 20 points
Other Parts Discussed in Thread: TVP70025I, TVP7002

The ALC registers (RGB) maintains a value that determines an offset value to be written to the course/fine offset register. The datasheet seems to specify two different registers for the this purpose, 'fine offset' page 14 -vs- 'course offset' page 40. Please clarify.

 

Ref, TI data sheet: SLES232A –JUNE 2008–REVISED APRIL 2010

From page 14 of Datasheet…

Automatic Level Control (ALC)

The ALC circuit maintains the level of the signal to be set at a value that is programmed at the fine offset I2C

register. It consists of a pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by

the I2C register at subaddress 26h.

The ALC circuit needs a timing pulse generated internally but the user should program the position properly. The

ALC pulse must be positioned after the clamp pulse. The position of ALC pulse is controlled by ALC placement

I2C register at address 31h. This is available only for internal ALC pulse timing. When using an external clamp

pulse, the fine clamp and the ALC both start on the leading edge of the external clamp pulse. Therefore, it is

recommended to keep the external clamp pulse as long as possible.

 

 

From Page 40 of Datasheet…

 

Blue Digital ALC Output LSBs

Subaddress 23h Read only

7 6 5 4 3 2 1 0

Blue ALC Out [7:0]

Blue ALC Out [7:0]: Eight LSBs of 10-bit filtered digital ALC output for Blue channel. The corresponding two MSBs are located at

subaddress 27h. With the internal ALC loop enabled, the ADC dynamic range can be maximized by adjusting the coarse offset settings

based on the ALC read back values. See registers 1Eh–20h for analog coarse offset control. If large adjustments are made to the analog

coarse offset control, adequate time must be allowed for the ALC to converge prior to reading of this register. ALC delay requirements

depend on the ALC NSV filter settings and the video input line rate. A delay of 30ms should be adequate for a 480i input with an NSV

setting of 1/64. ALC NSV filtering can be increased following final coarse offset adjustment. See Reg28h for more information on ALC filter

settings. Twos-complement value.

  • 0
    TI__Expert 6120 points

    Hello Michael,

    The coarse offset refers to an analog offset implemented before the ADC.

    The fine offset refers to a digital offset implemented after the ADC.

    The TVP70025i includes an automatic level control (ALC) algorithm to control the fine digital offset but not the coarse analog offset.

    If you want to automatically adjust the coarse analog offset, you'll need to implement an ALC algorithm in the backend processor.

    Regards,

    Jim

  • 0 in reply to James Nave
    Prodigy 20 points

    Hello Jim,

    Summary of VGA Flickering Problem:

     

    In a fine Moiré pattern (alternating white/black pixels) and flickering phenomenon is observed.  In using a magnifying glass to look at the screen the white pixels in the pattern are dimming randomly giving a flickering effect.  The flickering does have a horizontal component to it so it appears to be across some portion of a horizontal line.  The flickering is gray so there is not a color component to it (seems to happen on RGB in same proportion).

     

    Input is VGA (RGB) with separate Hsync and Vsync signals.

     

    PC graphics
    format

    pixel resolution
    (hor. x vert.)

    Frame rate
    (Hz)

    Line rate
    (kHz)

    Pixel rate
    (MHz)

    Video Standard

    XGA

    1024 x 768

    59.920

    47.816

    63.5

    VESA CVT 0.79M3

     

     

     

    So far the only setting that impacts the flickering is to set the coarse gain (or combo of coarse and fine gain) to 1.6.  This is above the recommended maximum coarse gain of 1.3 for 0.7Vpp signals.

     

    The values in the RGB coarse offset registers that result in ALC register values ~210 are in the 0-3 range which seems far from the 0x10 default value.  This is the case with a gain of 1.3 or 1.6.  This seems pretty far away  from the 0x10 default value.

     

     

    Questions we have:

     

    1.       Has TI run across this flickering problem before? And if so what is the cause and fix.

    2.       Why is a gain of 1.3 the recommended max?

    3.       How does the ALC impact the fine offset.  Can we get a general explanation of how this circuit works?

    Does the coarse offset of 0-3 sound reasonable?

     

     

     

    TVP70025 values Units
    Npd (number of pixel delay)
    Clock latency     		 18 Pixels TVP70025 data sheet, page 22, figure 6
    Npd=18 and the figure shows 13 also
    the power-on default value is 13 (0x0D).
    pixel times, difficult to understand and 13
    looks correct and 18 pixels is shifted left.
    XGA units
    Format number: 10 n.a.
    DMT ID n.a. EDID ID
    STD 2 Byte Code n.a. EDID ID
    CVT 3 Byte Code TBD EDID ID
    Scan Type /
    Blanking    		 non-interlaced
    normal blanking    		 n.a.
      Horizontal Sync Polarity NEGATIVE Active Level
    Hor Frequency 47.81626506 kHz
    Active Horizontal 1,024 Pixels
      Back 152 Pixels
      Front 48 Pixels
      Pulse Width 104 Pixels
      Horizontal pixel clocks per line 1328 Pixels
      Vertical Sync Polarity POSITIVE Active Level
    Ver Frequency 59.92013165 Hz
      Active Vertical  768 Lines
      Back 23 Lines
      Front 3 Lines
      Pulse Width 4 Lines
      Vertical Time 798 Lines
    Pixel Clock 63.5 MHz
    Total Pixels per line: 1,328 Pixels
    TVP70025
    Register    		 Reference Clock 27 MHz
    TVP70025
    Register    		 I2C
    sub-
    Addr    		  
    Sync Detect Status 14h 95h
    Lines Per Frame Status 37h 1Eh
    38h 03h
    Clocks Per Line Status 39h 35h
    3Ah 02h
    HSYNC Width 3Bh 2Ch
    VSYNC Width 3Ch 04h
    Item  I2C
    SUBADDRESS          		  DEFAULT
    VALUE    		  TVP70025
    REGISTER NAME      		 Direction   Comment
    1  00h    02h    Chip Revision    R   02h TVP70025I revision number = 02h
    2  01h    67h    H-PLL Feedback Divider MSBs    R/W   53h 1328 TVP70025 data sheet p.15, table 2
    3  02h    20h    H-PLL Feedback Divider LSBs    R/W   00h TVP70025 data sheet p.15, table 2
    4  03h    A8h    H-PLL Control    R/W   58h TVP70025 data sheet p.27, table 2, Kvco = 85, Icp = 3
    5  04h    80h    H-PLL Phase Select    R/W   80h TVP70025 data sheet p.28
    6  05h    32h    Clamp Start    R/W   06h
    7  06h    20h    Clamp Width    R/W   10h
    8  07h    20h    HSYNC Output Width    R/W   68h 104
    9  08h    00h    Blue Fine Gain    R/W   20h   New value 00h, No Fine Gain
    10  09h    00h    Green Fine Gain    R/W   20h   New value 00h, No Fine Gain
    11  0Ah    00h    Red Fine Gain    R/W   20h   New value 00h, No Fine Gain
    12  0Bh    80h    Blue Fine Offset MSBs    R/W   80h   New value = 70h, Fine Offset= -10h
    13  0Ch    80h    Green Fine Offset MSBs    R/W   80h   New value = 70h, Fine Offset= -10h
    14  0Dh    80h    Red Fine Offset MSBs    R/W   80h   New value = 70h, Fine Offset= -10h
    15  0Eh    5Bh    Sync Control 1    R/W   16h    
    16  0Fh    2Eh    H-PLL and Clamp Control    R/W   2Eh    
    17  10h   5Dh    Sync On Green Threshold    R/W   58h
    18  11h   20h    Sync Separator Threshold    R/W   40h
    19  12h   00h    H-PLL Pre-Coast    R/W   01h
    20  13h   00h    H-PLL Post-Coast    R/W   00h
    21  14h   00h    Sync Detect Status    R   95h CVT: 0.79M3 expect 95h
    22  15h   04h  Output Formatter    R/W   04h
    23  16h   11h    MISC Control 1    R/W   11h
    24  17h   03h    MISC Control 2    R/W   10h Data Enable output on pin 22
    25  18h   00h    MISC Control 3    R/W   01h Data clocked on falling edge
    26  19h   00h    Input Mux Select 1    R/W   00h
    27  1Ah   C2h    Input Mux Select 2    R/W   CAh External 27 MHz clock
    28  1Bh   77h    Blue and Green Coarse Gain    R/W   88h   New value=BB, Set Coarse Gain to1.6
    29  1Ch   07h    Red Coarse Gain    R/W   08h   New value=0B, Set Coarse Gain to1.6
    30  1Dh   00h    Fine Offset LSBs    R/W   00h  
    31  1Eh   10h    Blue Coarse Offset    R/W   10h   2's Comp. 01h=1      00h=0         20h=-0      21h=-1    22h=-2 New value=05, Then S/W Dec. til Reg23<21h
    32  1Fh   10h    Green Coarse Offset    R/W   10h   New value=05, Then S/W Dec. til Reg24<21h
    33  20h   10h    Red Coarse Offset    R/W   10h   New value=05, Then S/W Dec. til Reg25<21h
    34  21h   0Dh    HSOUT Output Start    R/W   0Ch 12 subtract 5 based on TVP70025 DS figure 6
    and Larry Taylor at TI (214-567-326)
    35  22h   08h    MISC Control 4    R/W   08h   change to 00, disable macrovision stripping
    36  23h   00h    Blue Digital ALC Output LSBs    R   00h   S/W Reads and Decriments REG 1E until < 21h
    37  24h   00h    Green Digital ALC Output LSBs    R   00h   S/W Reads and Decriments REG 1Funtil < 21h
    38  25h   00h    Red Digital ALC Output LSBs    R   00h   S/W Reads and Decriments REG 20 until < 21h
    39  26h   80h    Automatic Level Control Enable    R/W   80h
    40  27h   00h    Digital ALC Output MSBs    R   00h   S/W Reads should be 2Ah, High order coarse ofset bits=20h
    41  28h   53h    Automatic Level Control Filter    R/W   53h
    42  29h   08h    Reserved    R/W   08h  
    43  2Ah   07h    Fine Clamp Control    R/W   87h
    44  2Bh   00h    Power Control    R/W   00h
    45  2Ch   50h    ADC Setup    R/W   50h
    46  2Dh   00h    Coarse Clamp Control    R/W   00h  
    47  2Eh   80h    SOG Clamp    R/W   80h  
    48  2Fh   8Ch    RGB Coarse Clamp Control    R/W   8Ch  
    49  30h   04h    SOG Coarse Clamp Control    R/W   04h  
    50  31h   5Ah  ALC Placement    R/W   18h TVP 70025, p. 44, PC graphics setting
    51  32h   18h    Reserved    R/W   18h  
    52  33h   60h    Reserved    R/W   60h  
    53  34h   03h    Macrovision Stripper Width    R/W   03h  
    54  35h   10h    VSYNC Alignment    R/W   01h
    55  36h   00h    Sync Bypass    R/W   00h  
    56  37h–38h   00h    Lines Per Frame Status    R   1Eh 798 Expected values based on CVT_0.79M3 
    57   00h       03h    
    58  39h–3Ah   00h    Clocks Per Line Status    R   35h 565 Pixels/line = #pixels x (27MHz/Pixel clk)
    59   00h       02h  
    60  3Bh   00h    HSYNC Width    R   2Ch 44  
    61  3Ch   00h    VSYNC Width    R   04 4  
    62  3Dh    03h    Line Length Tolerance    R/W   06h
    63  3Eh   04h    Reserved    R/W   04h  
    64  3Fh   00h    Video Bandwidth Control    R/W   00h  
    65 40h 2Ch  AVID Start Pixel    R/W   12h 274 Write to SA: 40h first and SA:41h second updates after MSB (41h) is written.
    66 41h 01h  AVID Start Pixel    R/W   01h    
    67 42h 2Ch  AVID Stop Pixel    R/W   12h 1,298 Write to SA: 42h first and SA:43h second updates after MSB (43h) is written.
    68 43h 06h  AVID Stop Pixel    R/W   05h    
    69  44h   05h    VBLK Field 0 Start Line Offset    R/W   03h 3
    70  45h   05h    VBLK Field 1 Start Line Offset    R/W   00h
    71  46h   1Eh    VBLK Field 0 Duration    R/W   1Eh 30
    72  47h   1Eh    VBLK Field 1 Duration    R/W   00h
    73  48h   00h    F-bit Field 0 Start Line Offset    R/W   00h  
    74  49h   00h    F-bit Field 1 Start Line Offset    R/W   00h  
    75  4Ah–4Bh   16E3h    1st CSC Coefficient    R/W   E3
    76         16
    77  4Ch–4Dh   024Fh    2nd CSC Coefficient    R/W   4F
    78         02
    79  4Eh–4Fh   06CEh    3rd CSC Coefficient    R/W   CE
    80         06
    81  50h–51h   F3ABh    4th CSC Coefficient    R/W   AB
    82         F3
    83  52h–53h   1000h    5th CSC Coefficient    R/W   00
    84         10
    85  54h–55h   FC55h    6th CSC Coefficient    R/W   55
    86         FC
    87  56h–57h   F178h    7th CSC Coefficient    R/W   78
    88         F1
    89  58h–59h   FE88h    8th CSC Coefficient    R/W   88
    90         FE
    91  5Ah–5Bh   1000h    9th CSC Coefficient    R/W   00
    92         10
    93  5Ch–5Dh   0000h    Reserved    R/W   00
    94         00
    95  5Eh–FFh   0000h    Reserved    R/W   00
    96         00
  • 0 in reply to Michael Korejwo
    TI__Expert 6120 points

    Hello Michael,

    For a 0.7Vpp input, using a coarse gain greater than 1.3 may cause the input signal to clip at the 1Vpp input of the ADC.

    The ALC is a first-order recursive algorithm that drives the difference between the measured backporch and target backporch to zero by adjusting the fine digital offset.

    I'll have our TVP7002 expert respond to your VGA flickering issue when he returns to the office on Tuesday.

    Regards,

    Jim

  • 0 in reply to James Nave
    TI__Genius 16810 points

    Michael,

    The fine offset sets the final target, or output black level, of the ALC.

    Flickering in a high frequncy test pattern is typically due to incorrect ADC sampling phase.  Try adjusting the HPLL phase select setting in REG 04h.

    Regards,

    Larry