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AFE58JD48: When PLL_MODE = 80X, does AFE58JD48 JESD support 2-Lane mode?

APPLO ZHANG
Intellectual 515 points
Part Number: AFE58JD48

When PLL_MODE = 80X, does AFE58JD48 JESD support 2-Lane mode?

Thanks！

  • 0
    TI__Expert 4701 points

    Hi,

    In 80X mode, the 4 ADCs data is sent to one JESD lane. So to get data from all the 16 ADCs, you will need 4-lanes. In case if you are using demod then it is possible to get data for all the 16 ADCs in 2-lanes using 80x mode with decimation factor of 4 when mixer is enabled. 

    Regards,

    Shabbir

  • 0
    Intellectual 515 points

    Thank you very much for your prompt reply.

    I have another question:

    When MIXER enable, Decimation =3, is it possible to use PLL_MODE =160X so that JESD supports 2lane mode? I have not seen any similar examples in the manual. If so, can you explain the settings, similar to Table 64?

    Thanks!

  • 0 in reply to APPLO ZHANG
    TI__Expert 4701 points

    Hi,

    What is your ADC clock frequency? For 160x mode, the max clock speed supported is 62.5MHz. If your clock frequency is less than 62.5MHz then you can use 160x mode to get data of all the chs on 2 lanes.

    You can drop me a mail and I can share a tool that shows the output pattern sequence under different use condition set by the user. Reach out to me at: 

    support_us_afe_tx@list.ti.com

    Regards,

    Shabbir