Part Number: ADC12DJ800
Hi team,
One of our customer's issues, could you please give your comments.
Above is the setting of the Vivado JESD204B of xilinx. What I don't understand is the red line area above, rx_data[127:0], why it's only 128 bits. ADC12DJ800, I choose JMODE 0 mode, this mode F (frame) is fixed at 8, multiframe is 4 to 256, Step is 4. I set F to 8 and K to 4. My device is ADC12DJ800, dual channel.
This dual channel mode, as shown below, A0 to A9, B0 to B9, Add T. Dual channel should be 256 data. Why is the rx_data [127:0] in JESD204B in Vivado only 128 bits? This does not correspond to the pattern on this table.
Here is my ADC12DJ800 register configuration where I set the Short and Long Transport Test Mode. However, the data from rx_data[127:0] from JESD204B in ivado is not fixed. Could you help me figure out what to do with this?
Here's the ila waveform I grabbed
Best Regards,
Amy Luo
