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DAC38J84: FIFO empty alarm in all lines.

Juan Fernandez
Prodigy 10 points
Part Number: DAC38J84

Hi all,

I am trying to configure the DAC38J84 in a custom board. I have the DAC PLL locked and the PLL serdes locked but I am getting the FIFO empty error no matter what I try.

This is my configuration of the JESD IP core:

  

 

To sum up:

  • LMF=841 mode.
  • DACCLK reference is 400MHz.
  • I am sending 256 bits at a rate of 62.5MHz (tx_core_clk_out).
  • My line rate is then 256*62.5MHz*10/8/8 = 2.5Gbps
  • Interpolation = 8 as I have 250MHz DAC input rate and 2000MHz DAC output rate.
  • JESD clock is 125MHz (2000 DAC PLL out / 16 = 125MHz) following the relation JESD_div_clk = INTERPOLATION*L/M = 8*8/4 = 16.
  • I assume I am operating at quarter rate since line rate is 2.5Gbps and serdes PLL is 2.5GHz.
  • I am not using SYSREF.

Parameters like K, F are the same in the JESD IP core and in the DAC.

I configure the DAC PLL as in the next figure (I am not using the tool to configure the DAC as I am working with a custom board, but I use the image to explain my configuration).

 

 

After configuring the DAC, I can see the tx_ready signal at high level coming from the JESD IP core. Also the signal tx_start_of_multiframe is toggling so I assume the JESD IP core is sending data from the FPGA (we are using a Zynq Ulstrascale+).

 My questions are:

  • ¿Am I configuring the clocks properly? Specially JESD clk which I am not sure the relation it has to have with the other clocks.
  • In my case, it is correct to assume that DAC clk in is 250MHz? I assume this because I am sending packets of 256 bits at a rate of 62.5MHz, equivalent to send 64 bits (1 samples of 16 bits per converter) at a rate of 250MHz. If this is correct, I assume that the interpolation is 8 since the output of the PLL DAC is 2000MHz.
  • I managed to generate a simple tone at 500MHz using the NCO at a quarter of the DAC PLL output frequency (2000MHz) so I assume the DAC PLL is configured as I wanted.
  • Is it correct the assumption of operating at quarter rate? I base my configuration in this table:

But I would like to understand this table also, how is defined “one data sample” in this table?

 

Having said all this, why I have the FIFO empty error in all the 8 lines?

Thank you so much in advance.

  • 0
    TI__Mastermind 20155 points

    Hi Juan,

    This device is subclass 1 only. It needs a sysref to align internal dividers for the jesd link. If there is no sysref present then this could cause the empty fifo issues. Do you have the ability to supply a sysref signal?

    Thanks, Chase

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi Chase, 

    Thanks for your response. We can generate a sysref periodic signal from our PLL. 

    So, even if you configure the DAC to not use sysref signal it is necessary to provide it with one?

    Which is the relation that the frequency of the sysref must fulfill to work properly?

    I just notice that when I set initial state to 0000 and release the jesd reset (0x4A -> 0xFF01) I get 0x03 in the alarm register for all lines (read_error and read_empty)

    Also, the SYNCB pin is set to 0 at this moment.

    I change my K from 20 to 2 to be able to generate a sysref clock from my PLL, now it is running at 25MHz. 

    LMFC = linerate/10/K/F = 2500/10/2/1 = 125MHz

    sysref = LMFC/n = 125/5 = 25MHz

    is it problematic to have sysref present before configuring the DAC?

    Thanks!

    Juan.

  • 0 in reply to Chase W
    Prodigy 10 points

    Hi again,

    I have another question related to SYSREF, I am providing a SYSREF signal to my FPGA JESD core and other to my DAC38J84 chip generated from my PLL. I generated these two signals as normal outputs of the PLL so the SYSREF is always running from the first moment I configure this PLL in charge of generate of the main clocks of the design. Is there any problem in working this way? I know that having active SYSREF may cause some degradation in the spectrum of the generated signals but could it cause not to get the link up? (SYNCB signal is not going high again...).

    PD: the SYSREF frequency is now 5MHz which I assume it fullfils the requirement of being linerate/10/K/n/F (K=2, F=1).

    Thanks,

    Juan. 

  • 0 in reply to Juan Fernandez
    TI__Mastermind 20155 points

    Hi Juan,

    If you have K set as 2, it may not allow adequate RBD for the link to come up correctly. Is it possible for you to set K as 16 and modify sysref accordingly?

    Thanks, Chase