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DAC38J84: FIFO Errors

Jhoneldrick Millares
Prodigy 140 points
Part Number: DAC38J84
Other Parts Discussed in Thread: LMK04828

Hi Jim,

I have four DAC38J84s clocked by an LMK04828 and an FPGA (the ZCU102) attempting to establish JESD204B link between all four of them.

LMFS = 2441

Line Rate = 9.8304 Gbps

Sampling Frequency = 245.76 MHz with One-Shot Sysref (triggered via the SYNC request pin on the LMK).

Strangely enough, I'm able to establish a link and transmit on 2 of my four DACs. All DACs have the same config, and the LMK04828 has the same register values for the clocks going to each DAC.

For the two DACs that don't establish link, I'll get FIFO Alarms on the two active lanes after clearing and reading the following registers:

Lane 2 (0x66) = 0x3 or 0xb or 0x703

Lane 4 (0x67) = 0x3 or 0xb

I know these mean a SERDES FIFO Read or Write errors, but what kind should we change to address these? We don't think its our configs since they are all the same. I've attached them below. We have two separate files since we are using our own tool to program our DACs and LMK (and we've verified that our SPI reads and writes work).

  • 0
    Prodigy 140 points

    This is the waveform of the SYNCB signals from each DAC (0 to 3 starting from the top) after issuing a sysref request.

    DACs 3 and 4 seem perfectly fine, deasserting SYNC about 40 cycles after sysref.

    DAC 0 receives the SYSREF and SYNC asserts at the same time as DACs 3 and 4 but it never deasserts SYNC.There is a FIFO Read error on this DAC.

    DAC 1 asserts SYNC 6 cycles earlier than the other 3 DACs and never deasserts it.There is a FIFO Read error, Code Synchronization, 8b/10b not in table, and 8b/10b disparity error for this DAC's lanes.

  • 0 in reply to Jhoneldrick Millares
    TI__Genius 9695 points
    Hi,

    What are the results if you use continuous SYSREF instead of single shot SYSREF? If all 4 DACs work with continuous SYSREF then you can adjust the timing between SYSREF and device clock at the failing DACs to ensure reliable capture of SYSREF.

    Also note that SYSREF should be DC coupled to LMK if using one shot SYSREF and the common mode must be ~500mV.

    Thanks,
    Eben.
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 140 points
    Hi Ebenezer,

    Thanks for your reply. A few questions:

    1. Would triggering sysref multiple times be equivalent to this technique?
    2. What is this timing adjustment and what registers would I program?
    3. Could you please provide a configuration file for continuous sysref operation?
    ---
    LMFS = 2441
    Line Rate = 9.8304 Gbps
    Lanes Active: RX2 and RX3

    We have DACs on:
    DCLKOUT0 SDCLKOUT1 (DAC 0 - Non functioning)
    DCLKOUT8 SDCLKOUT9 (DAC 1 - Non functioning)
    DCLKOUT10 SDCLKOUT11 (DAC 2 - Functioning)
    DCLKOUT12 SDCLKOUT13 (DAC 3 - Functioning)

    and the FPGA on:
    DCLKOUT4 SDCLKOUT5

    Unconnected:
    DCLKOUT2 SDCLKOUT3
    DCLKOUT6 SDCLKOUT7
    ---
  • 0 in reply to Ebenezer Dwobeng
    Prodigy 140 points
    Continuous SYSREF did not work - I still get an 0x3 for Lanes 2 and 3 at 0x66 and 0x67 on DACs 2 and 3.
    It is repeatable across boards.

    I also misspoke earlier - we are using an 8 Pulse SYSREF triggered by the SYNC_REQ pin.
  • 0 in reply to Jhoneldrick Millares
    Prodigy 140 points

    Resolved. 0x3 corresponds to the JESD204B lanes never being driven by the FPGA due to a faulty constraint file not properly mapping the pins on the FMC connector.