ADC3424: LVDS data signal waveform issue

菊井良則

Prodigy 130 points

Part Number: ADC3424

In our LVDS interface from AD3424 to FPGA, we have LVDS data signal issue.

(Please check attached file.)

Now, we are investigating the termination setting in FPGA.

But, can't we have some issue about ADC output setting?

If you have some idea to debug this issue, could you tell me your suggestion?

LVDS data signal issue.xlsx

This LVDS data signal was output by following ADC resister writing.

address data
0x4006 0x01
0x470A 0x01
0x4009 0x00
0x400E 0x1C
0x400F 0x70
0x400A 0x55
0x400B 0x55
0x4006 0x02

Thank you.

Yoshinori Kikui

over 2 years ago

0 Rob Reeder over 2 years ago

TI__Mastermind 45670 points

Hi,

The LVDS data signal issue, it due to reflections.

Please make sure the FPGA internal terminations options are enabled.

Regards,

Rob

0 Rob Reeder over 2 years ago in reply to Rob Reeder

TI__Mastermind 45670 points

Hi,

Keep in mind, if the LVDS traces go through vias and/or a connector this will also add to the degraded signal integrity.

Regards,

Rob

0 菊井良則 over 2 years ago in reply to Rob Reeder

Prodigy 130 points

Thank you for your answer.

But, we confirmed FPGA internal termination (100ohm) is enable.

And, in LVDS DCLKP/M and DD1P/M, the trace length and the number of via is same.

I investigated the spec of LVDS output block (Please check attached file.).

In ADC3424, is the LVDS output circuit block as same as attached image?

Can't we change the LVDS output setting (i.e. drive strength)?

LVDS Output.xlsx

Thank you.

Yoshinori Kikui

0 Chase W over 2 years ago in reply to 菊井良則

TI__Mastermind 24550 points

Yoshinori,

Please try with modifying register 0x25. This LVDS SWING field will impact the drive strength. Unfortunately there is no description for this so I cannot recommend if setting 0xFF means max drive strength or not. I personally would try values 0x0F, 0xF0, and 0xFF and see if you can determine which improves or degrades the swing. How is this being measured? It is possible that what you are seeing is a result of the scope probe, can you check that they are tuned adequately?

Thanks

0 菊井良則 over 2 years ago in reply to Chase W

Prodigy 130 points

Thank you for your information. We will try LVDS SWING register.

Do you mean LVDS output source current of ADC3424 is not fixed value, but adjustable value?

If I can do it, I want to know the current range we can adjust by LVDS SWING register.

Thank you.

Yoshinori Kikui

+1 Rob Reeder over 2 years ago in reply to 菊井良則

TI__Mastermind 45670 points

Yes, correct, see datasheet snippet attached below.

Thank you,

Rob

0 菊井良則 over 2 years ago in reply to Rob Reeder

Prodigy 130 points

Thank you for your answer.

If I need more information, I will create other question.

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ADC3424: LVDS data signal waveform issue