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Hi team,
I have a question regarding Figure 21 and Table 15 of the datasheet.
As per the ADS1256 specifications, after switching the multiplexer channel, I think it is necessary to wait for conversion (discard data) for the DRDY period shown in Table 15. Should I assume that this is only for data rates above 3750SPS, and for data rates below 3750SPS, the data can be retrieved continuously and does not need to be discarded?
Thank you for your help.
Regards,
Taito Takemura
Hi Taito Takemura,
Can you please post the customer name and project info in the Notes section of the Thread Tracking Toolkit?
-Bryan
Hi Bryan,
I've added customer's info. Please let me know if any information is missing.
Regards,
Taito Takemura
Hi Taito Takemura,
Thank you for providing this information
As per the ADS1256 specifications, after switching the multiplexer channel, I think it is necessary to wait for conversion (discard data) for the DRDY period shown in Table 15. Should I assume that this is only for data rates above 3750SPS, and for data rates below 3750SPS, the data can be retrieved continuously and does not need to be discarded?
There is a difference between "switching the multiplexer" (Fig 19, Table 14) and "data settling time" (Fig 21, Table 15)
If the customer is cycling through the multiplexer inputs, then the ADC will automatically wait for the data to settle before toggling the DRDY pin to indicate that new data is ready. See the highlighted section below from the datasheet
However, if a step input occurs during data capture - for example, you are measuring a 1V signal and then instantaneously the input signal on that same channel changes to 5V - the ADC will require some time to provide settled data. This is what is captured in Figure 21 and Table 15.
So no, they do not need to discard data if they are just cycling through the multiplexer, but they might have to discard data if a step input occurs during the conversion process. However, this is true for all delta-sigma ADCs
-Bryan
Hi Bryan,
Thank you for your answer.
> if a step input occurs during data capture - for example, you are measuring a 1V signal and then instantaneously the input signal on that same channel changes to 5V - the ADC will require some time to provide settled data.
Is it correct to understand that when step input occurs, the number of data determined in Table 15 must be discarded at speeds of 3750 SPS or higher?
Regards,
Taito Takemura
Hi Taito Takemura,
Is it correct to understand that when step input occurs, the number of data determined in Table 15 must be discarded at speeds of 3750 SPS or higher?
In general, yes, this is correct. When a step input occurs for data rates < 7500 SPS, you will have to wait for the current conversion to complete if a conversion is in progress, and then the next conversion should be settled data. For data rates >=7500 SPS, you will have to wait for the current conversion to complete if a conversion is in progress, and then wait the number of DRDY periods specified in Table 15 for settled data
-Bryan