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Input and Output Termination Requirement (RT - 50ohms to AVcc)

Hafiz Haja
Intellectual 500 points

Part Number: SN75DP139

Hi, In a new design we are using SN75DP139 for DP++ to DVI TMDS level shifting application. Please address below queries: 1. Main link of SN75DP139 is interfaced to a DP++ source. DP++ signal is ac coupled to the input pins of SN75DP139 similar to evaluation board schematics of SN75DP139. There is 3.3V pull up termination option via 50ohm in evaluation board for DP++ signals before ac coupling capacitor. Please confirm the requirement of 50 ohm pull up to AVCC (3.3V) before ac coupling capacitor. 2. TMDS output of SN75DP139 is directly interfaced to a Xilinx/AMD FPGA TMDS receiver bank. Please confirm whether SN75DP139 has internal 50 ohm pull up to AVcc (3.3V). If not we have to provide it in our circuit. In evaluation board schematic there is no pull up option shown for SN75DP139 TMDS outputs. 3. Also there is no common mode voltage values given in datasheet for TMDS / CML output from SN75DP139. Regards Hafiz Haja

  • 0
    TI__Guru**** 191321 points

    Hi,

    Hafiz Haja said:
    1. Main link of SN75DP139 is interfaced to a DP++ source. DP++ signal is ac coupled to the input pins of SN75DP139 similar to evaluation board schematics of SN75DP139. There is 3.3V pull up termination option via 50ohm in evaluation board for DP++ signals before ac coupling capacitor. Please confirm the requirement of 50 ohm pull up to AVCC (3.3V) before ac coupling capacitor.

    The pullup resistors are for TMDS termination only and are not part of the DisplayPort signal termination. For DP++ source, you do not need this external 50ohm termination network.

    Hafiz Haja said:
    2. TMDS output of SN75DP139 is directly interfaced to a Xilinx/AMD FPGA TMDS receiver bank. Please confirm whether SN75DP139 has internal 50 ohm pull up to AVcc (3.3V). If not we have to provide it in our circuit. In evaluation board schematic there is no pull up option shown for SN75DP139 TMDS outputs. 3. Also there is no common mode voltage values given in datasheet for TMDS / CML output from SN75DP139.

    If the Xilinx/AMD FPGA TMDS receivers requires to be AC coupled, then SN75DP139 would require to have external 50ohm pullup to 3.3V termination. There is no common mode voltage value given in the datasheet since it is expected that the common mode voltage will be set by the HDMI sink. Please note the external termination along with the FPGA internal termination produces double termination and therefore will reduce the signal into the FPGA input. If 50-Ω is used, then DP139's voltage swing must be increased to compensate for the double termination.

    Thanks

    David