• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 46 subscribers
  • Views 187 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

AFE5832LP: About the reception of LVDS data of AFE5832LP chip

AFE5832LP: Data reception problem

wupang17
Prodigy 65 points
Part Number: AFE5832LP
Other Parts Discussed in Thread: AFE5832,

When I used the test mode of AFE5832, I used the toggle mode. Why is the output of the AFE chip correct at the beginning of a short period of time, but after a while it becomes very messy?
In addition, when I used the AFE chip's all-0 or all-1 test mode, it was the same situation, only in the beginning of a period of time, the output of each channel of AFE was correct, and then the data changed not all 0 or all 1, but a jumble of numbers. What do you think is the reason? Does the AFE chip fail some time after writing to the register and setting to test mode? If this is the case, what should I do?

  • 0
    TI__Expert 3735 points

    Hi,

    1) Are you testing this on EVM or your system ?

    2) What is the sequence you followed after power up ?

    3) What is the ADC_CLK speed ? 

    4) How are you capturing ? Can you please provide capture details ?

    Changing test mode does not cause this issue .

  • 0 in reply to Sachin H K
    Prodigy 65 points

    Hi Sachin,

    Thanks for your reply!
    Regarding question 1: I do not have an EVM for AFE5832LP, so I did not test it
    About question 2: After the chip is powered on, my order is according to the manual, as shown in the figure below.
    About question 3: The ADC_CLK I originally used is 100MHZ, so I also doubted whether the frequency is too high will cause problems, I reduced it to 20MHZ, the result is the same phenomenon.
    About question 4: I store the data transmitted from AFE through serial unstring to fifo, and then upload it to the host computer.
    This phenomenon is not caused by switching test modes, but the problem occurs in every test mode, no matter what mode I use, the phenomenon is normal at the beginning, and then after a period of time, the data is wrong.
    Do you need some additional operations? I have read the chip manual in detail, but still nothing.

    Looking forward to your reply!

    Thanks!

  • 0 in reply to Sachin H K
    Prodigy 65 points

    In addition, I have a big question is, for the register value of the AFE chip, will it fail after writing for a while?
    Because after power-on and initialization, the phenomenon is normal, proving that my register Settings are correct, but the subsequent data seems to be because the register value is invalid? Do you think that's the reason?

  • 0 in reply to wupang17
    TI__Expert 3735 points

    To summarize your problem , Initially data is coming out correctly and after you write some register it is going bad . 

    - What is the register write you are doing which causes this issue ?

    - Also are you following device initialization as per datasheet section 10.4

    - Are  your supplies able to give the expected current for device ? You can check the supply voltage to confirm is there any voltage drop because of lower current clamp.

  • 0 in reply to Sachin H K
    Prodigy 65 points

    Thanks for your reply! I'm sorry if I gave you the wrong impression.
    In the beginning my data was normal, but after a while it was abnormal, during which time I did not change any register values.
    I mean, could the register value be invalidated in the meantime?

  • 0 in reply to wupang17
    TI__Expert 3735 points

    The register setting will remain as long as you don't reset the device or power down. You can read out the register value from device to confirm the register settings.