I encountered difficulties in using DAC38RF8xEVM. After the JESD204b link was established, SYNC kept toggling, and DAC had no signal output.
Clock circuit adopts On-Board VCXO Clock Mode (CMODE4) in DAC38RF8xEVM to change the VCXO of the board to 120MHz and change the register Settings. The VCO frequency is 2.5GHz, the clock output to the DAC DACCLK+ frequency is 2.5GHz, the SYSREF+ is 9.765625MHz, the bypass DAC's PLL.
JESD204b config
Lane Rate =12500.00MHz
Dual DAC,real input,4 Lanes,1x interpolation is 2500
Serdes Configured to Full Rate
Serdes clock predivider = 2
Serdes PLL Vrange = 0
Serdes PLL Multiplier = 10
2 TX L-M-F-S-Hd = 82121 Dual DAC, single link
K=32
pSCR= 0
N=16
The following is the DAC reg
The FPGA jesd204b ip configure
localparam [7:0] pDID = 8'h00;
localparam [3:0] pADJCNT = 4'h0;
localparam [3:0] pBID = 4'h0;
localparam pADJDIR = 1'b0;
localparam pPHADJ = 1'b0;
localparam pSCR = 1'b0;
localparam [4:0] pL = 5'b0111;
localparam [7:0] pM = 5'b00001;
localparam [1:0] pCS = 2'd0;
localparam [4:0] pN = 5'd15;
localparam [4:0] pNt = 5'd15;
localparam [4:0] pS = 5'd1;
localparam pHD = 1'b1;
localparam [4:0] pCF = 5'd0;
localparam [7:0] pRES1 = 8'h00;
localparam [7:0] pRES2 = 8'h00;
