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ADS8355: ADS8355 SDO setup / hold timing related to SCLK

Peter Jesinger
Prodigy 10 points
Part Number: ADS8355

In the datasheet there is a number for T_D_CKDO given as 19.5 ns which means that new data on SDO is valid 19.5ns after the falling edge of SCLK, but there is no number for the time of how long old data is valid after the rising edge of SCLK.

Do you have a minimum value there?

If the minimum would be 0ns, data would only be valid for 0.5ns when using a 50 MHz (period 20ns) clock on SCLK. Is this indeed the case? 

  • 0
    TI__Guru 66466 points

    Hi Peter,

    Thank you for your post.

    We do not have a minimum hold time for SDO, but of course it would be non-zero. However, since clock is coming from the host, there should still be enough time in most cases for the old data to latch before the SDO transition occurs as seen by the host. Have you been able to read data successfully so far using the interface as-is?

    Are you using one or two SDOs in your application? Is it possible to slow down the interface to less than the maximum 50 MHz?

    Alternatively, (I'm not completely sure this would work), you may be able to bring SCLK low before nCS goes low, such that the leading edge becomes a rising edge (both nCS and SCLK must be held high for a minimum of tCONV). This might allow you to treat the interface as if it were SPI Mode 00 and read data on the clock rising edge. The MSB (D15) is clock out by the nCS falling edge, so with SCLK going low before nCS, the leading edge could still be used to latch the data while the trailing edge (i.e. falling edge) would continue to shift data out as normal.

    Regards,

    Ryan