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ADC3661: Output data

ttd
Mastermind 8780 points
Part Number: ADC3661


Dear Technical Support Team,

SLVDS for ADC3661 has 2-wire, 1-wire,1/2-wire output mode.

According to each timing diagram,  is following output timing from sampling to Digital data correct? 

10MSPS = 0.1us for sampling clock.

2-wire ⇒ (0.1us +tPD+tCD) * 2 from sampling to output

1-wire,1/2-wire ⇒0.1us+tPD+tCD from sampling to output

Best Regards,

ttd

  • +1
    TI__Intellectual 2280 points

    Hi ttd,

    What you have for 1-wire and 1/2-wire appears to be correct.

    For 2-wire, I believe multiplying by 2 should only happen for the sample clock period. When also multiplying tPD and tCD by 2, that is being overlapped with the doubled period of the sample clock.

    So, it would be 2*(0.1 us) + tPD + tCD

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Mastermind 8780 points

    Hi Drew,

    Thank you for your reply.

    I understand output timing you mentioned without DDC.

    I'd like to confirm clock frequency about 10MSPS and 16bit.

    If I have misunderstanding, could you fix?

    2-wire ⇒ FCLK=5MHz,DCLKIN and DCLK = 40MHz、DA0/DA1 and DB0/DB1 =80MHz(80MBPS)

    1-wire ⇒ FCLK=10MHz,DCLKIN and DCLK = 80MHz、DA0 and DB0 =160MHz(160MBPS) 

    1/2-wire ⇒ FCLK=10MHz,DCLKIN and DCLK = 160MHz、DA0 =320MHz(320MBPS) 

    Best Regards,

    ttd

  • +1 in reply to ttd
    TI__Intellectual 2280 points

    Hi ttd,

    Yes, what you have here is correct.

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Mastermind 8780 points

    Hi Drew,

    By the way, is there any advantage of 1/2-wire compared to 2-wire other than the reduction of 2 pins(DB0P and DB0M)?

    Since data rate is twice that of 2-wire, the design with the FPGA interface becomes more difficult.

    So I thought 2-wire would be safer if there is enough for the number of pins on FPGA  and the board area.

    Best Regards,

    ttd

  • +1 in reply to ttd
    TI__Intellectual 2280 points

    Hi ttd,

    At 10 MSPS, it may not matter much. Two wire should give slightly better performance than half-wire since it is spec'd in the datasheet. In contrast, half-wire saves power. One wire mode gets is a pretty good mix of the two while reducing the frequency needed for DCLKIN that is required for half-wire mode.

    Some of this can also depend on desired input frequency and fpga.

    Regards,

    Drew