When The Feature Select Register SDO[2:0] is set to '011', there are an extra 9 bits that Table 13 in the datasheet states will be on the SDO signal. All timing diagrams in the datasheet only allude to 16 bits being shown after the 16th SCLK bit when reading from the channels (Figures 83-86 e.g.). I am assuming that those plots were shown assuming SDO[2:0] = 000, in which case SDO would be '0' after that?
Can you verify that for SDO[2:0] set to 011 that we should be sending a total of 16 (for command phase) and 25 more to collect all of the data that is available?
If CS is removed after the last bit of the Conversion result (bit 9 in Table 13) will the ADS8688 default back to waiting for another transaction and just ignore the fact that the extra 9 bits were not shifted out?
But if we want to read those extra bits we would just leave CS asserted and continue to pulse SCLK?
