Hi team,
We used DAC8775. For /LDC signal, we use it in Synchronous Mode now.
DAC8775 Datasheet said, if certain delay “SYNC rising edge->LDAC falling edge” 33ns is not met, invalid data will be loaded. How about the invalid data?
Because we found that /LDAC signal may be corrupted in some EMC case, does it mean that will affect the output of DAC?
Thanks
Lillian