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Synchronizing Multiple DAC5670s

darren morrow
Prodigy 10 points


I am looking at using two DAC5670 to drive tx I/Q data.  I have questions about how to guarantee alignment of the two DACs.

(1)  Reading the data sheet leads me to believe that the two DACs running in parallel have the possibility of coming up out of synch due to the initial state of the dividers.  Is this true?

(2)  Does the "RESTART" input reset the two clock dividers?  if so, is it internally synchronized to DACCLK?  Can the "RESTART" be used to sychronized multiple DACs?

(3) In the block diagram, the DLL looks like it aligns data to the internal 1/4 clock, while in the timing diagram, it looks like the DLL aligns to the internal 1/2 clock.  Is timing diagram right?

(4) Assuming all data and clock lines to the two DACs are tightly matched and constrained, should I be able to detect a miss-aligned condition base on the phase difference of the two "DLYCLK" signals?

(5) If miss-aligned condition can detected can you suggest method for aligning?

 

I've got some ideas about how to deal alignment, but wanted TI advice/suggestions before running off to re-invent the wheel.

 

Thanks,

Darren

 

 

 

 

  • 0
    TI__Guru 62930 points

    Darren,

    Sorry for the delay.  I have discussed this with Bryan with ACAT support.

    At the time of release this type of use was not intended.  Currently with the support structure in place, we are having difficulty accessing additional data to help understand internal operation.  This is still ongoing.  Unfortunately this process is slow. 

    With respect to question 4) The data is aligned to DACCLK/4.  This is indicated in Figure 15 as well.

    Regards,

    Wade

  • 0 in reply to Wade Vonbergen
    TI__Guru 62930 points

    Darren,

    I meant to add a little more info on the restart pin.

    The restart pin essentially resets the DLL delay to its starting position.   This should cause it to transition to its nearest locking solution upon release.

    Regards,

    Wade