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ADS4449: No signal output at bit1 and bit2 in test pattern mode

BO ZHI ZHANG
Prodigy 20 points
Part Number: ADS4449

Hi,

I am facing that there is no ADS4449 output signal at bit 1 and bit 2 while in test pattern mode. Please refer to the attachment for the two different phenomenon at ADS4449 output. Looks like there is no any signal applyed at bit 1 and 2, it's just the inphase common noise I think(or other possible reason). Which there is abvously a very clear P&N signal at other bits.

I have asked this issue last week, and also refer to the content, https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1131411/ads4449-databit-fluctuation, by your kindly advise.

But its still got the issue after I checked all the registers mentioned in the above page.

I wonder if there is any other reasons could casuse the kind of issue. 

Attachments for your reference:

1. ADS4449 normal output(p&n), normal bits

2. ADS4449 unusual output(p&n), bit 1 & 2

3. First stage

4. second stage

5. ADC input stage

Thank you for your assistance and look forward to hearing from you soon.

  • 0
    TI__Mastermind 39600 points

    Hi Bo Zhi,

    I am not clear on what is being referred to at on this oscope capture.

    2. ADS4449 unusual output(p&n), bit 1 & 2

    Can you please give more context?

    Also, the second and first stage in your schematic pictures above are the same circuit. 

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 20 points

    Hi Reeder,

    Thank you for your reply.

    That's me make it simple.

    I probed these four pairs of signal, DAB1P,1M,DAB2P, 2M, DCD1P, 1M, DCD2P, 2M, directly from ADS4449 output.(in test pattern mode, for AC always write 1 and BD always write 0)

    But it got the following signal on the oscope, which is abviously no signal.

    And for other bits, DAB 0, DAB 3, DAB4...,DAB13, DCD0, DCD3, DCD4....DCD13, are way better than bit 1 and bit 2. (please refer to  no.1 picture I posted)

  • 0 in reply to BO ZHI ZHANG
    Prodigy 20 points

    I checked it with lower clock frequency, 125MHz, and the results are the same.

    And I also check the bias at these output pins.

    The Vcm at bit1 and bit2 (DAB1P, 1N, DCD1P, 1N, DAB2P, 2N, DCD2P,2N) are also drop down to around 300mV.

    Below is the normal one for reference, which Vcm is around 1V.

  • 0 in reply to BO ZHI ZHANG
    TI__Intellectual 2280 points

    Hi Bo Zhi,

    Thank you for this extra detail. We will try to set this up and see if we see the same issue early next week and will get back with you then.

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    TI__Mastermind 39600 points

    Hi Bo Zhi,

    Thank you for the details, I assume the ADC is connected to an FPGA?

    Is the FPGA on another board?

    Can you check the power supply at the ADC/device to make sure you have +1.8V?

    Does the common mode voltage on the digital outputs come back to 1.05V when you are NOT in test pattern mode?

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 20 points

    Hi Rob,

    Thank you for your reply.

    Yes, the ADC is connected to a FPGA through a RMC connector.

    I have checked the three voltages 3.3V, 1.9V, 1.8 for ADC.

    The common mode voltage on the bit 1 and bit 2(DAB, DCD, 1&2 ) is not 1.05V, but around 250mV when it's not in test pattern mode.

    And In contrast to other digital outputs which act normal, they're at 1.05V.

    It's seems that bit 1 & 2 doesn't properly maintain at the correct common mode voltage whether it's in test pattern mode or not.

  • 0 in reply to BO ZHI ZHANG
    TI__Intellectual 2280 points

    Hi Bo Zhi,

    Thank you for this information. If Vcm is not correct for all operation modes, it possibly hints toward something hardware related. Would it be possible to share your schematic?

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Prodigy 20 points

    Hi Harrell

    Thank you for your reply.

    Please refer to the following pictures for ADC related schematic. (ADS4449 IBAS8LW)

    • ADC power (3.3, 1.9, 1.8)

    • ADC analog input and digital output

    • ADC SPI

    I have checked the voltage at VCMA, VCMB, VCMC, VCMD which is all around 1.15V. 

  • 0 in reply to BO ZHI ZHANG
    TI__Intellectual 2280 points

    Hi Bo Zhi,

    Thank you for sending this over. Does the scope look exactly the same for both bit 1 and bit 2 output data?

    Would it be possible to send over your SPI writes for the "Always write 1" bits?

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Prodigy 20 points

    Hi Harrel,

    For your question one, yes, both bit 1 and bit 2 output waveform are the same.

    Please refer to the attachments for the code.

    BTW, I have three ADS4449 in one PCB board, so there would be like named adc1, adc2, adc3 in the code 

    Fullscreen ads4449.c Download 
    /*
 * cdcm6208.c
 *
 *  Created on: 2023�~6��29��
 *      Author: machi
 */
#include <ads4449.h>
uint8_t wlmx_ads4449_1_data[SEND_BUFFLEN_TO_ADS4449] = {0};
uint8_t rlmx_ads444_1_data[SEND_BUFFLEN_TO_ADS4449] = {0};
soft_spi_dev ads4449_1 =
{
     .cs_port       = ADS_1_CS_PORT,
     .cs_pin        = ADS_1_CS_PIN,
     .cs_idle       = CS_IDLE_ADS,
     .clk_port      = ADS_1_CLK_PORT,
     .clk_pin       = ADS_1_CLK_PIN,
     .clk_idle      = CLK_IDLE_ADS,
     .mosi_port     = ADS_1_MOSI_PORT,
     .mosi_pin      = ADS_1_MOSI_PIN,
     .mosi_idle     = CS_IDLE_ADS,
     .miso_port     = ADS_1_MISO_PORT,
     .miso_pin      = ADS_1_MISO_PIN,
     .clk_dur       = CLK_DUR_ADS,
     .cs_latency    = CS_LATENCY_ADS,
     .databits_len  = TOTAL_BITS_ADS,
     .data_len      = SEND_BUFFLEN_TO_ADS4449,
	 .cpol 			= 1,
	 .cpha			= 0,
     .wdata_ptr      = wlmx_ads4449_1_data,
     .rdata_ptr      = rlmx_ads444_1_data
};

uint8_t wlmx_ads4449_2_data[SEND_BUFFLEN_TO_ADS4449] = {0};
uint8_t rlmx_ads444_2_data[SEND_BUFFLEN_TO_ADS4449] = {0};
soft_spi_dev ads4449_2 =
{
     .cs_port       = ADS_2_CS_PORT,
     .cs_pin        = ADS_2_CS_PIN,
     .cs_idle       = CS_IDLE_ADS,
     .clk_port      = ADS_2_CLK_PORT,
     .clk_pin       = ADS_2_CLK_PIN,
     .clk_idle      = CLK_IDLE_ADS,
     .mosi_port     = ADS_2_MOSI_PORT,
     .mosi_pin      = ADS_2_MOSI_PIN,
     .mosi_idle     = CS_IDLE_ADS,
     .miso_port     = ADS_2_MISO_PORT,
     .miso_pin      = ADS_2_MISO_PIN,
     .clk_dur       = CLK_DUR_ADS,
     .cs_latency    = CS_LATENCY_ADS,
     .databits_len  = TOTAL_BITS_ADS,
     .data_len      = SEND_BUFFLEN_TO_ADS4449,
	 .cpol 			= 1,
	 .cpha			= 0,
     .wdata_ptr      = wlmx_ads4449_2_data,
     .rdata_ptr      = rlmx_ads444_2_data
};

uint8_t wlmx_ads4449_3_data[SEND_BUFFLEN_TO_ADS4449] = {0};
uint8_t rlmx_ads444_3_data[SEND_BUFFLEN_TO_ADS4449] = {0};
soft_spi_dev ads4449_3 =
{
     .cs_port       = ADS_3_CS_PORT,
     .cs_pin        = ADS_3_CS_PIN,
     .cs_idle       = CS_IDLE_ADS,
     .clk_port      = ADS_3_CLK_PORT,
     .clk_pin       = ADS_3_CLK_PIN,
     .clk_idle      = CLK_IDLE_ADS,
     .mosi_port     = ADS_3_MOSI_PORT,
     .mosi_pin      = ADS_3_MOSI_PIN,
     .mosi_idle     = CS_IDLE_ADS,
     .miso_port     = ADS_3_MISO_PORT,
     .miso_pin      = ADS_3_MISO_PIN,
     .clk_dur       = CLK_DUR_ADS,
     .cs_latency    = CS_LATENCY_ADS,
     .databits_len  = TOTAL_BITS_ADS,
     .data_len      = SEND_BUFFLEN_TO_ADS4449,
	 .cpol 			= 1,
	 .cpha			= 0,
     .wdata_ptr      = wlmx_ads4449_3_data,
     .rdata_ptr      = rlmx_ads444_3_data
};

//uint8_t init_6208_fpga[INIT_6208_REG_LENGTH][SEND_BUFFLEN_TO_6208] =
//		{
//				{0x00 , 0x00 , 0x01 , 0xB9},
//				{0x00 , 0x01 , 0x00 , 0x00},
//				{0x00 , 0x02 , 0x00 , 0x17},
//				{0x00 , 0x03 , 0x08 , 0xF0},
//				{0x00 , 0x04 , 0x20 , 0xD4},// 0x20 , 0xD4
//				{0x00 , 0x05 , 0x01 , 0x32},//LVDS->CMOS
//				{0x00 , 0x06 , 0x00 , 0x05},
//				{0x00 , 0x07 , 0x00 , 0x32},
//				{0x00 , 0x08 , 0x00 , 0x05},
//				{0x00 , 0x09 , 0x00 , 0xD2},
//				{0x00 , 0x0A , 0x00 , 0x50},
//				{0x00 , 0x0B , 0x00 , 0x00},
//				{0x00 , 0x0C , 0x00 , 0xC2},
//				{0x00 , 0x0D , 0x00 , 0x50},
//				{0x00 , 0x0E , 0x00 , 0x00},
//				{0x00 , 0x0F , 0x00 , 0x00},
//				{0x00 , 0x10 , 0x00 , 0x00},
//				{0x00 , 0x11 , 0x00 , 0x00},
//				{0x00 , 0x12 , 0x00 , 0x00},
//				{0x00 , 0x13 , 0x00 , 0x00},
//				{0x00 , 0x14 , 0x00 , 0x00},
//				{0x00 , 0x15 , 0x00 , 0x00}
//		};

int init_ads4449(int map)
{
    /*
     * Initialize data of LMX2820 by map 0 or 1
     *      */

//	uint16_t temp16 = 0;
//    current_map = map;
    soft_spi_dev *spi_dev =(map == 1)? &ads4449_1 : ((map == 2)? &ads4449_2 : &ads4449_3);
    init_sofspi_pin(spi_dev);

//    spi_dev->wdata_ptr[0] = 0;
//    spi_dev->wdata_ptr[1] = 0;
////    write_register(spi_dev);
//
//    for (i = 0 ; i < INIT_6208_REG_LENGTH-1 ; i++) {
//        for(j = 0 ; j < SEND_BUFFLEN_TO_6208 ; j++) {
//
//            if (map == 0)
//                spi_dev->wdata_ptr[j] = init_6208_fpga[i][j];
//            else
//                spi_dev->wdata_ptr[j] = init_6208_adc[i][j];
//
//
//        }
     //   printf();
//        write_register(spi_dev);
//        delay(50);
//    }
	return 0;
};
int read_ads4449_reg(int map, uint8_t reg)
{
    soft_spi_dev *spi_dev =(map == 1)? &ads4449_1 : ((map == 2)? &ads4449_2 : &ads4449_3);
    write_ads4449m_reg(map , 0 , 1);
    spi_dev->wdata_ptr[0] = reg;
    spi_dev->wdata_ptr[1] = 0;
    read_register(spi_dev);
    write_ads4449m_reg(map , 0 , 0);
    return ((spi_dev->rdata_ptr[0] << 8) | spi_dev->rdata_ptr[1]) & 0xFF ;
};

int write_ads4449m_reg(int map, uint8_t reg , uint8_t value)
{
    soft_spi_dev *spi_dev =(map == 1)? &ads4449_1 : ((map == 2)? &ads4449_2 : &ads4449_3);
    spi_dev->wdata_ptr[0] = reg;
    spi_dev->wdata_ptr[1] = value & 0xFF;
    write_register(spi_dev);
	return 0;
}
    ads4449.h
    Fullscreen my.c Download 
    /*
 *
 * Xilinx, Inc.
 * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A 
 * COURTESY TO YOU.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
 * ONE POSSIBLE   IMPLEMENTATION OF THIS FEATURE, APPLICATION OR 
 * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION 
 * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE 
 * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION
 * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO 
 * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO 
 * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE 
 * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY 
 * AND FITNESS FOR A PARTICULAR PURPOSE.
 */

/*
 * 
 *
 * This file is a generated sample test application.
 *
 * This application is intended to test and/or illustrate some 
 * functionality of your system.  The contents of this file may
 * vary depending on the IP in your system and may use existing
 * IP driver functions.  These drivers will be generated in your
 * SDK application project when you run the "Generate Libraries" menu item.
 *
 */
#include <cdcm6208.h>
#include <ads4449.h>
#include <stdio.h>
#include "xparameters.h"
#include "xil_cache.h"
#include "xgpio.h"
#include "gpio_header.h"
#include "mcugpio.h"
#include "softspi.h"
#include "led.h"
int main () 
{
   int adc_reg_addr[14]	  = { 0x00 , 0x25 , 0x2B , 0x31 , 0x37 , 0xA9 , 0xAC , 0xD6 , 0xD7 , 0x59 , 0x71 , 0x89 , 0xA1 , 0x45 , 0x42 , 0x3D , 0xCF , 0xFE };

   int adc1_reg_write[14] =	{ 0x02 , 0x01 , 0x02 , 0x01 , 0x02 , 0x00 , 0x00 , 0x80 , 0x0C , 0x80 , 0x80 , 0x80 , 0x80 , 0x10 , 0x08 , 0x20 , 0x08 , 0x00 };
   int adc2_reg_write[14] =	{ 0x02 , 0x01 , 0x02 , 0x01 , 0x02 , 0x00 , 0x00 , 0x80 , 0x0C , 0x80 , 0x80 , 0x80 , 0x80 , 0x10 , 0x08 , 0x20 , 0x08 , 0x00 };
   int adc3_reg_write[14] =	{ 0x02 , 0x01 , 0x02 , 0x01 , 0x02 , 0x00 , 0x00 , 0x80 , 0x0C , 0x80 , 0x80 , 0x80 , 0x80 , 0x10 , 0x08 , 0x20 , 0x08 , 0x00 };

   int adc1_reg_read[14]  =	{ 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 };
   int adc2_reg_read[14]  =	{ 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 };
   int adc3_reg_read[14]  =	{ 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 , 0x00 };

   int reg_cdcm = 0;
   int i=0;

   GPIO_initialize();
   Xil_ICacheEnable();
   Xil_DCacheEnable();

//   //GPIO test
//   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN1 ); //SCLK
//   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN2 ); //SDATA(MOSI)
//   GPIO_setAsInputPin( GPIO_PORT0, GPIO_PIN3 );	//SDOUT(MISO)
//   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN0 );	//SEN2(CS2)
//   while(1){
//	   for(i=0 ; i<10 ; i++){
//		   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN1 );
//		   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN2 );
//		   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN0 );
//		   usleep(10);
//		   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN1 );
//		   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN2 );
//		   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN0 );
//		   usleep(10);
//	   }
//	   sleep(1);
//   }

   init_led();

   //ADC CDCM PDN active low
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN8);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN8 );
   usleep(100000);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN8 );
   //ADC CDCM RESET active low
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN9);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN9 );
   usleep(100000);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN9 );
   //ADC CDCM SYNC active low
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN10);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN10 );
   usleep(100000);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN10 );

   //ADC1 PDN
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN11);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN11 );
   usleep(100000);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN11 );
   //ADC1 RESET
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN14);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN14 );
   usleep(100000);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN14 );

   //ADC2 PDN
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN12);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN12 );
   usleep(100000);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN12 );
   //ADC2 RESET
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN15);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN15 );
   usleep(100000);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN15 );

   //ADC3 PDN
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN13);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN13 );
   usleep(100000);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN13 );
   //ADC3 RESET
   GPIO_setAsOutputPin( GPIO_PORT0, GPIO_PIN16);
   GPIO_setOutputHighOnPin( GPIO_PORT0, GPIO_PIN16 );
   usleep(100000);
   GPIO_setOutputLowOnPin( GPIO_PORT0, GPIO_PIN16 );

   //Initialize CDCM
   init_cdcm6208(1);

   //Initialize ADCs
   init_ads4449(1);
   init_ads4449(2);
   init_ads4449(3);

   //Write ADC register values
   for( i=0 ; i<14 ; i++){
	   write_ads4449m_reg( 1 , adc_reg_addr[i] , adc1_reg_write[i] );
	   usleep(10000);
	   write_ads4449m_reg( 2 , adc_reg_addr[i] , adc2_reg_write[i] );
	   usleep(10000);
	   write_ads4449m_reg( 3 , adc_reg_addr[i] , adc3_reg_write[i] );
	   usleep(10000);
   }

while(1)
{
	for( i=0 ; i < 14 ; i++ ){
		adc1_reg_read[i] = read_ads4449_reg( 1 , adc_reg_addr[i] );
		adc2_reg_read[i] = read_ads4449_reg( 2 , adc_reg_addr[i] );
		adc3_reg_read[i] = read_ads4449_reg( 3 , adc_reg_addr[i] );
	}
	reg_cdcm = read_cdcm_reg( 1 , 21);
	sleep(1);
}


   Xil_DCacheDisable();
   Xil_ICacheDisable();
   return 0;
}

  • 0 in reply to BO ZHI ZHANG
    TI__Intellectual 2280 points

    Hi Bo Zhi,

    Thanks for sending that over! The register data looks good to me. Has the data readback confirmed everything is being written correctly?

    Regards,

    Drew

  • 0 in reply to Drew Harrell
    Prodigy 20 points

    Hi Drew,

    Thanks for your reply.

    Yes, everything is readback correctly, so I am confusing what could be the possible reason causing this kind of issue.

    Actually, I have made four boards, and total 12 ADS4449s(three on each) have this problem.

    So from your perspective so far, the hardware and software seems no issue for you?

    For me, the difference between bit 1,2 and the others is weird to me cause they are all in the same condition. 

    Could you kindly suggest that any action I could test? or any other possible way I could think of.

    Thanks again for your help.

  • +1 in reply to BO ZHI ZHANG
    TI__Intellectual 2280 points

    Hi Bo Zhi,

    I have looked at this on our EVM in the lab. I noticed upon bring up that bits 1 and 2 looked the same as what you are seeing. The GUI we have has a check box for always write 1. When I clicked on that, bits 1 and 2 became "active" and showed a common mode similar to the other output data bits. I have attached the register configuration for this state. Please try this and let me know if bits 1 and 2 come up. You should just be able to open the file as .txt

    Always_1ABCD_Readout.cfg

    Best regards,

    Drew

  • 0 in reply to Drew Harrell
    Prodigy 20 points

    Hi Drew,

    Thank you for providing that.

    I checked the registers in register map in datasheet which mentioned need to be set logic high after reset or power-up.

    I found that I didn't write ''1'' for D0 in register address AC. And after changing ''0'' to ''1'' in address AC, it came alive in bit1 & 2.

    So it's kind of undetermined or undefined address issue I think.

    Btw, I tried the register configuration you provided, and turned out that the bit1,2 issue dissapeared but came to bit 0. So maybe it's another undetermined issue which I found it doesn't write ''1'' in D7 in adress 89 and A1.

    Anyway, thank you again for your help, Drew. I am very appreciate. 

  • 0 in reply to BO ZHI ZHANG
    TI__Intellectual 2280 points

    Bo Zhi,

    I missed that as well in the register writes you sent over a noticed that in the new configuration I sent.

    Regarding the bit 0 "turning off", this should be due to the default state of the part being 13-bit with overrange on the LSB. This can be disabled, resulting in 14-bit output, by setting bit 4 of register 45h.

    Best regards,

    Drew