hello，
I am using FPGA to configure AFE58JD48. I want to verify the JESD204B link. However, after configuring some registers, I found that the JESD204B IP CORE in the FPGA did not show any received data. Please help to confirm if my register configuration is correct.
FPGA side, I found rx_islockedtodata signal is always 0 , this should indicate that JESD204B IP core cannot recover clock from serial data by CDR.
Here is my current register configuration:
Begin
SPI_DIG_EN = 1 00_0001 # global reset, self clear
SPI_DIG_EN = 1 C5_4000 # according to "12.2 Device initialization"
SPI_DIG_EN = 1 D0_0001 #
SPI_DIG_EN = 1 DE_00C3 #
SPI_DIG_EN = 1 DF_0040 #
SPI_DIG_EN = 1 1E_0003 #
SPI_DIG_EN = 1 12_0005 #
SPI_DIG_EN = 1 2A_0800 #
SPI_DIG_EN = 1 12_0000 #
SPI_DIG_EN = 1 11_FFFF #
SPI_DIG_EN = 1 25_0002 #
SPI_DIG_EN = 1 11_0000 #
SPI_DIG_EN = 1 12_000A # according to "10.3.8.1.2 JESD 80X Mode (or 4-Lane Mode)" NOTE
SPI_DIG_EN = 1 29_0001 #
SPI_DIG_EN = 1 31_03C0 #
SPI_DIG_EN = 1 34_091F #
SPI_DIG_EN = 1 35_01C0 #
SPI_DIG_EN = 1 36_0007 #
SPI_DIG_EN = 1 30_8002 #
SPI_DIG_EN = 1 30_8006 #
SPI_DIG_EN = 1 31_03D0 # test
SPI_DIG_EN = 1 32_0040 #
SPI_DIG_EN = 1 12_0000 #
End
thanks！
