ADS1220: Precisions on the conversion time and delays

Hi Etienne,

I had a bit of trouble understanding what was asked, but I hope this helps answer some of your questions. 

Etienne Paternoster said:

It is said that in normal mode continuous conversion mode, the first conversion starts 210*Tclk after the end of the SPI start message, but there is no mention of a delay between the end of a sample measurement and the DRDY signal, is it below Tclk?

The timing diagram in in section 8.5.4 shows that there is a 2*Tclk delay in the DRDY signal. 

Etienne Paternoster said:

Is it correct to assume that the actual time (during which the measurement is done) is the same between continous and single-shot, and that the 98 Tclk difference is the sum of before/after delays?

No, conversion time is different between continuous and single shot mode. In single shot mode, there is a 50us wake-up time for the internal oscillator, and the modulator clears data and is reset each time which accounts for a longer conversion time. In continuous conversion mode, there is an initial 210*Tclk delay on the first conversion, and subsequently each conversion takes what is stated in Table 11 of the data sheet. The modulator is continuously running during continuous conversion mode as opposed to being reset each time as in single conversion mode, accounting for slightly different conversion times. 

Best Regards,

Angel

Hi,

Thanks for your answer, I'm actually trying to differentiate what you call "modulator running" (my "time during which the measurement is done") and "conversion time" (the values on table 11). I do understand that this badly defined "conversion time" is higher in single-shot compared to continuous, since in continuous mode "conversion time" and "modulator running" are the same but in single-shot there must be some starting/ending actions. My concern is whether or not the "modulator running" time is the same in signle-shot and continuous mode, which I cannot find explicitly written.

I understand these Fig.61/62 as saying "If DRDY was already low, it will pulse for 2*Tclk"; I do not see any indication as to when the start of these "2*Tclk" occurs in relation to the end of the "modulator running" period.

Thanks,

Étienne.

Hi Etienne,

The conversion times for single-shot mode and continuous conversion are defined different, which may be why there is some confusion.

Continuous conversion mode data rates are timed from one DRDY falling edge to the next DRDY falling edge.

The first conversion starts 210 · Tclk after the last SCLK falling edge of the START/SYNC command, meaning that the first conversion takes longer to be ready. This would be your "starting action" in continuous conversion mode. After that, the conversion time is defined as one DRDY falling edge to the next DRDY falling edge with the modulator constantly running, which is the time shown in Table 11.

Single-shot mode data rates are timed from the last SCLK falling edge of the START/SYNC command to the DRDY falling edge and rounded to the next t(CLK).

For single-shot mode, in case the internal oscillator is used, an additional oscillator wake-up time of up to 50 µs must be added, which would be what you are referring to as the "starting/ending action". 

In single-shot mode the internal oscillator starts to power up at the first SCLK rising edge of the START/SYNC command, while in continuous conversion mode (apart from the first conversion) the internal oscillator is already powered on which translates to a slightly shorter actual conversion time. 

The time it takes to have a conversion ready is slightly different for both of these modes, which is what is shown in Table11.

Timing for the length of the conversion period in SS mode would typically be 50us (oscillator startup) + (204850 tclk periods) * (1/4.096MHz).

Timing for the length of the conversion period in continuous conversion mode, after the first conversion (DRDY falling edge to the next DRDY falling edge) would be (204768 tclk periods) * (1/4.096MHz).

The tclk period is based on the internal oscillator frequency (tclk = 1/fclk) when the internal oscillator is used, or by the external clock frequency when an external clock is used.  The tclk for the internal oscillator is designed around 4.096MHz clock so the tclk period is 1/4.096MHz.  However, the internal oscillator time can vary as much as  +/-2% which is directly proportional to the total time of conversion.

DRDY indicates when a new conversion result is ready for retrieval. When DRDY falls low, new conversion data are ready. DRDY transitions back high on the next SCLK rising edge. When no data are read during continuous conversion mode, DRDY remains low but pulses high for a duration of 2 · t(MOD) prior to the next DRDY falling edge. The DRDY pin is always actively driven, even when CS is high.

Best Regards,

Angel

Dear Angel,

Could you get back on the timing question about the delay before getting the DRDY rising edge (if DRDY is already low)?

In other words, what is the delay between the end of the conversion and the DRDY rising edge?

Regards,

Hi,

Conversion data is ready when DRDY falls low, not when DRDY transitions high. 

DRDY will then transition back to high on the next SCLK rising edge.

This is stated in the data sheet:

During continuous mode, data is ready when DRDY falls low, not on the rising edge. DRDY will transition to high 2*t(MOD) before data is ready, and DRDY transitioning back to low is what indicates data is ready. 

Etienne Paternoster said:

I do not see any indication as to when the start of these "2*Tclk" occurs in relation to the end of the "modulator running" period.

As stated DRDY will transition back to high after a data ready on the next SCLK rising edge, this is unrelated to the modulator clock. 

In Continuous conversion mode DRDY will transition high 2*Tclk before data is ready, and then transition back to low when data is ready. 

Not really sure what else you are looking for here. 

Best Regards,

Angel

Hi,

I realised that I failed to mention that I'm only concerned with external oscillator operations (3MHz in my case, but since everything is proportional to Tclk I don't think it should matter here), and my DRDY is idle before the end of conversion.

I'm trying to differentiate 2 different kinds of events:

- The interface events, timed with last SCLK of SPI command on one side and DRDY falling edge on the other;

- The signal measuring period, during which the input signal is integrated, which has a beginning and an end within the boudaries of the interface events.

Here is a concrete example: Using the ADC in single-shot mode, I need to activate my sensor before the measure, and I need to precisely know the elapsed time between my action and the beginning of the measuring period, using as timestamp the DRDY of the ADC. To achieve this, I need to know:

- The delay between the end of the measuring period and the fall of DRDY;

- The precise length of the measuring period.

Other example: I'm studying the noise level of my sensor, which is integrated over the measuring period; The noise from my sensor is thus squarely linked to the length of the sample recording, which I need to precicely know.

Coming back to the datasheet, I understand that in continuous mode the signal is being measured 100% of the time, so the time between 2 DRDY falling edges is exactly the length of the signal measuring period. For single-shot mode, the datasheet only tells me about the time between the interface events, but nothing about the signal measuring period.

So the 2 things that I want to understand are:

- What is the delay between the end of the signal measuring period and the DRDY falling edge?

- Is the length of the measuring period the same between continuous conversion and single-shot, and if it isn't, what is it for single-shot?

Thanks,

Étienne.

Hi Bob,

Thanks you for this answer, it settles my query about the single-shot sampling time.

Considering the computation delay, I read the datasheet as explaining that there is a pulse in case DRDY is already low, but I don't see any explicit link to a computation time; Can you confirm that it is exactly the computing time or is it an educated guess?

Regards,

Étienne.

Hi,

This is exactly my use case, my sensor requires pre-sampling actions and I'm using the DRDY for datation and synchronisation, hence my need to precisely understand the sampling time and sync in relation to DRDY. Knowing that the sampling end to DRDY delay is within 2*tmod is enough for me.

Thank you for your help!

Regards,

Étienne.