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ADC122S021: Input channel right after CS falling edge

Kazuki Itoh
Genius 10810 points
Part Number: ADC122S021
Other Parts Discussed in Thread: ADC128S102

Hi team,

  1. Could you let me know the input channel right after the /CS falling edge?
    Is it default (CH1) or the channel set in the previous conversion cycle?
  2. Do you recommend to keep /CS low when the device is not used?
    Or, it is better to assert low only when the device is used?
  3. 7-8us after the /CS is held high, my customer saw the DOUT automatically held from low to high.
    Is this behavior expected? 

Best regards,

Kazuki Itoh

  • +1
    TI__Expert 8896 points

    Hi Kazuki-san,

    Thanks for your questions.

    1. The default is IN1. This is the first conversion result after power-up and the subsequent conversion results will depend on the control register bits set in the previous cycle.
    2. This depends on the customer need and application. Please see the datasheet section below:
    3. On page 16 of the datasheet, it is mentioned "The ADC output data (DOUT) is in a high impedance state when CS is high and is active when CS is low." 

    I hope this helps.

    Best regards,

    Samiha

  • 0 in reply to Samiha Sharif
    TI__Genius 10810 points

    Hi Samiha-san,

    Thank you so much. Could you please help me to double check the my understanding below is correct?

    The output channel at the specific cycle shown in yellow box is:

    1. CH1
    2. CH2
    3. CH1
    4. CH1
    5. CH1
    6. CH1

    Best regards,

    Kazuki Itoh 

  • 0 in reply to Kazuki Itoh
    TI__Expert 8896 points

    Hi Kazuki-san,

    The output channels for pattern 1 look correct but in pattern 2, it should be identical to pattern 1. 

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    TI__Genius 10810 points

    Hi Samiha-san,

    The difference between the patter1 and 2 is /CS is toggling.

    You answered that the the input channel right after the /CS falling edge is IN1 to my initial question #1.

    Could you please elaborate on that? After CS toggling, does the register still remember the channel selected in the previous cycle, or just output default IN1?

    Best regards,

    Kazuki Itoh 

  • +1 in reply to Kazuki Itoh
    TI__Expert 8896 points

    Hi Kazuki-san,

    Oh! I missed that, thanks for pointing it out. When /CS toggles, the device is powering up after having been in power-down mode. The first conversion will be CH1 after /CS toggles, as this is the default at power-up.

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    TI__Genius 10810 points

    Hi Samiha-san,

    My customer sees the IN2 output selected in the previous cycle right after CS goes low. Could you please double check your answer on the EVM? 3Vdc is input to IN1 and and 0V is input to 0V.

    My customer wants to toggle CS cycle by cycle to address the bit shift issue.

    In that case, how my customer read IN2 data?

    Do you recommend to ignore the first cycle after CS goes low?

    Best regards,

    Kazuki Itoh

  • 0 in reply to Kazuki Itoh
    TI__Expert 8896 points

    Hi Kazuki-san,

    Could you clarify please? IN2 = 0V and IN1 = 3V? Did the customer probe the inputs to ensure that these are the correct values?

    Yes, if the customer wanted to read IN2 data, they would need to ignore the first DOUT data (this would default to IN1 data) and write IN2 address, and IN2 data would come out in the next DOUT cycle.

    Best,

    Samiha

  • 0 in reply to Samiha Sharif
    TI__Genius 10810 points

    Hi Samiha-san,

    Yes, IN1=3V and IN2=0V. They don't need to probe it as DC supply is connected to the input.

    My customer sees the DOUT is IN2 value after selecting IN2 in the previous cycle while toggling /CS every cycle as attached in the previous post.

    It doesn't match what you told me.

    That's why I'm requesting to double check on EVM.

    Best regards,

    Kazuki Itoh

  • 0 in reply to Kazuki Itoh
    TI__Expert 8896 points

    Hi Kazuki-san,

    Okay. I understand the confusion. Let me talk to the team and get back to you on this.

    Best,

    Samiha

  • 0 in reply to Kazuki Itoh
    TI__Expert 8896 points

    Hi Kazuki-san,

    This device does not have an EVM. So, I will test it with another device in the family. Please allow a few days for me to acquire the EVM and complete this testing. The datasheet language is a little confusing. Based on the customer's observations, my assumption is IN1 is the default after ADC power-up/power-cycle. But, the previous channel address is held when /CS is toggled, and this is why IN2 data is output when /CS is brought low again. 

    Best,

    Samiha

  • +1 in reply to Samiha Sharif
    TI__Expert 8896 points

    Hi Kazuki-san,

    Thanks for your patience. I had a chance to test the ADC128S102, an 8CH device in the same family. The customer's observation is correct. When a channel address is set in the previous /CS cycle, the next /CS cycle will output that channel data instead of defaulting to CH0 reading.

    An example test:

    I am reading CH0 DOUT (pink signal), set to 3.3V input:

    I leave the last config register address (DIN = green signal) as CH0 and raise /CS (yellow signal) high. When I pull /CS low, the first reading is still for CH0. Then, DIN address for CH3 is read in and the next DOUT is for CH3.

    I hope that helps.

    Best regards,

    Samiha

  • 0 in reply to Samiha Sharif
    TI__Genius 10810 points

    Hi Samiha-san,

    Thank you for the confirmation that my customer's observation is correct.

    But I don't understand your test results.

    Did you set the DIN to read CH3 and raise /CS high and then pulled /CS low and the first reading of the next cycle was CH3?

    Then, let's go back to the previous question.

    My customer wants to toggle /CS cycle by cycle to address the bit shift issue.

    Do you recommend to ignore the first cycle after /CS goes low?

    I believe that my customer doesn't need to ignore the first cycle as the next /CS cycle will output that channel data instead of default.

    Best regards,

    Kazuki Itoh 

  • 0 in reply to Kazuki Itoh
    TI__Expert 8896 points

    Hi Kazuki-san,

    Using a different channel example: if CH2 address is set and then /CS is raised high, the DOUT after /CS is low again will be CH2 data. So yes, your last statement is correct, the customer does not need to ignore the first DOUT result in an N+1 /CS cycle as the channel address that was set in N /CS cycle will be output on DOUT, not the default.

    Best,

    Samiha