• State Resolved
  • Locked Locked
  • Replies 4 replies
  • Subscribers 46 subscribers
  • Views 155 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADC08DJ3200EVM: Difficulty locking lanes with KCU105

Etienne Drouin
Prodigy 60 points
Part Number: ADC08DJ3200EVM

Hi everyone!

I'm trying to connect an ADC08DJ3200EVM to a KCU105 from Xilinx using the FMC connector. I have a FCM+ to FMC transposer allowing me to connect the two of them, in my configuration, I only use 8 lanes so the other lane allowed by using a FMC+ are not needed. I'm using the ADC12DJxx00 GUI to configure the EVM, here is a few configuration data: On-board clock source, Fs = 3200Msps, JMODE5, with a k value of 32 (same as in the FPGA configuration), JESD204B block control in Test mode ramp test mode, the FPGA clock with a divider of 32 and sysref divider of 160. In myt FPGA, the configuration is in RX mode with a resolution of 8, 8 lanes, 2 quads, GTH MGT, 1 refclk buffer, a data width of 64, f val of 1 and k val of 32, with a MGT ref clock of 100MHz. I think everything is in order, but I'm open to advise.

The problem is that I can't get any data. QPLL0 lock's and a clock is recovered from the JESD204 ip as the mgt_rx_usrclk2 is used for some ilas and they work fine. The rest of the FPGA works fine. I'm receiving some sysref and the realign count goes to 1 and doesn't change after that so the sysref is working as intented too. There is no other error other than the fact that rx_sync_n never goes high and no data comes.

Is there someone that can point me in the right direction with this? I can't find information about how to solve this anywhere.

Thank you!

Étienne

  • 0
    TI__Expert 4410 points

    Hello Étienne,

    Can you please confirm if you are using TI JESD IP or some custom FW? It sounds like the problem to me is that the SYNCb pin of the ADC might not being mapped correctly to the FPGA dev kit, can you please double check this in your FPGA FW. The ADC sync pin is mapped to H31 of the FMC+ connector. 

    One other thing you could try is using the software sync feature of the ADC which will allow you to control the sync of the ADC with spi writes to the part. To do this please look at registers JSYNC_N (0x203) and JCTRL (0x204). If this work it will narrow the problem down to sync related issue.

    Thanks,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    HI Eric,

    Yes I'm using the TI JESD IP for this. I've been able to make it work in loopback mode, but I'm now trying to make it work in RX mode only. I'm also going to confirm that the ADC sync is mapped on the right pin. In the Ilas data I get, I never see the sync signal changing value. 

    I didn't find the spi sync control in the registers you told me, only some configuration and a way to disable the sync input signal (making it ignore it?). I tried to change those configuration, but it didn't work. All that to say, it didn't seem to change anything.

    Thanks,

    Étienne

  • 0 in reply to Etienne Drouin
    TI__Expert 4410 points

    Hello Étienne,

    The registers to control the ADC sync would be...

    First program the SYNC_SEL field in the JCTRL regsiter (0x204) to enable software sync (value =2 for this field)

    Second you can use toggle the JSYNC_N bit inside the JSYNC_N register (0x203)

    Another thing to check is after programming the ADC please check the value of JESD_STATUS register (0x208) and verify the value reported.

    Lastly, you can also try and probe the sync signal on the evm itself and verify that the fpga is actually outputting a sync signal.

    Best,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 60 points

    Hi,

    I found the error. I did a beginner error and just didn't include de encoding in the line rate and put 6.4Gbp/s instead of 8Gbp/s. With this change in setting, I receive some data. I still have a few errors, but I'll work on them and make another post in the forum if needed. 

    Thanks for your help!

    Étienne