Hello : )
I'd like to interface this with a 2.5V bank on a Polarfire FPGA (the I/O's are less susceptible to latch-up with lower bank voltages). It's likely I'd power the device at 2.9V (so 0.2V higher than the 2.7V minimum supply).
Could you provide digital input and output characteristics at the 2.7V level? I'd just like to ensure it's compatible.
From the data sheet:
When IOVDD is 5V, the minimum high level input voltage is 2.1V
the minimum high level output voltage is 4.8V when sourcing 3mA
When IOVDD is 3.3V, the minimum high level input voltage is 2.2V
the minimum high level output voltage is 2.9V when sourcing 3mA
From this data I'd guess that with IOVDD at 2.7V, the high level input voltage would be around 2.3V? Would be awesome is it was still 2.2V.
Id also guess that the high level output voltage would be around 2.3V when sourcing 3mA ?
May need to consider just running the device at 3.3V and using level translators on the digital outputs.
Thanks for the help!
Adam
