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AFE58JD28: Synchronizing two AFE58JD28 AFEs

Matt Calvo
Genius 14655 points
Part Number: AFE58JD28

Hey Data Converters team,

I have a customer prototyping with the AFE58JD28 for a project and we were hoping you could help to provide guidance on how to properly synchronize two together. Please see a summary of our inquiry below!

I am posting here because it seems like there is discussion of this device on your E2E forum but If you prefer this discussion to be held off of this forum please let me know and I'll reach out directly as needed. Thanks!

We are planning to synchronize two AFE58JD28 AFEs together and want to know if the SYSREF signal coming in will synchronize them. In the datasheet it only states that the TX_TRIG signal will synchronize two chips but we are wondering if the SYSREF signal will also synchronize two chips based on the block diagram near the top of the datasheet. There are also other things that seem to imply that SYSREF will synchronize two chips but in the section about syncing two chips it only talks about the TX_TRIG pin. Can you help us find clarification on this?

Best regards,

Matt

  • 0
    TI__Genius 14655 points

    Hey DC team,

    Any updates here? Please let us know if you need any further information.

    -Matt

  • 0 in reply to Matt Calvo
    TI__Expert 4661 points

    Hi Matt,

    SYSREF signal will reset the LMFC clock. So this is standard way to synchronize and maintain deterministic latency across devices. You shall refer to section "Synchronization Using SYNC~ and SYSREF" of the datasheet. It explains which all blocks get reset on applying SYSREF signal.

    Other best way which most of the customers relies to match the latency of multiple devices is by looking at SYNC word at the device output (With demod enabled) which gets inserted in the data by the device on applying a TX_TRIG pulse. So basically JESD link get established using SYNC/SYSREF and use TX_TRIG for matching latency by looking at sync word. Also if you are applying SYSREF periodically and dont want demod to get disturbed then set JESD_RESET1 bit to "1".

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    TI__Genius 14655 points

    Thanks for the reply!

    I've passed this along to my customer and will have them comment back on this thread directly with any follow-up questions they may have.

    -Matt

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 60 points

    Shabbir,

    In the datasheet under "11.2 Device Initialization", it says that we must assert TX_TRIG as part of the power-up, initialization, and multi-chip synchronization.  Can we instead assert SYSREF for this purpose, as long as JESD_RESETx registers are configured for also resetting clocks/phases of non-JESD blocks?

    -Eric

  • 0 in reply to Eric G.
    TI__Expert 4661 points

    Yes that should be ok.

    Just for our alignment -> At system level, SYSREF will be generated by LMK and it will be periodically running. You may not want to reset demod on SYSREF. So TX_TRIG comes quite handy to tackle this situation. Even though SYSREF can do the job but better to have TX_TRIG connection also at system level to decouple demod with SYSREF.

    Thanks!

    Regards,

    Shabbir

  • 0 in reply to Shabbir Amjhera Wala
    Prodigy 60 points

    Shabbir,

    We don't use demod and we only strobe SYSREF once (not periodically).  The only reason we would have TX_TRIG connected would be for this initialization/multi-chip synchronization requirement on power-up.  So this does save us a little bit of complexity to utilize SYSREF for this purpose.

    Thank you for your help!

    -Eric