ADC3644: Power Up Sequecnce

Hirotsugu Kobayashi

Part Number: ADC3644

Hi team,

I use the ADC3644 with an external 1.6V reference. I attach the waveforms of each power supply and VREF.
It will take some time for VREF to stabilize, but is there any problem as long as each power supply and VREF are stabilized before the reset is released?
Does VREF need to be started later for AVDD and IOVDD?

Best regards,

over 1 year ago

0 Drew Harrell over 1 year ago

TI__Intellectual 2280 points

Hi,

Please reference Section 9.2 of the data sheet regarding power up sequencing. I have attached a screen shot below.

Best regards,

Drew

0 Hirotsugu Kobayashi over 1 year ago in reply to Drew Harrell

Mastermind 9590 points

Hi Drew,

I understand that diagram, but since REFBUF is internally pulled up, it rises at the same time as AVDD, so it does not look like this diagram. Please tell me the meaning of this diagram.
What effect will it have if ExtVREF fluctuates before the reset is released?

Best regards,

0 Drew Harrell over 1 year ago in reply to Hirotsugu Kobayashi

TI__Intellectual 2280 points

Hi,

Oh okay, my apologies. So, what is the VREF in the scope image you provided? Is that VREF from the internal reference from the device or is it the external VREF that you are providing?

Best regards,

Drew

0 Hirotsugu Kobayashi over 1 year ago in reply to Drew Harrell

Mastermind 9590 points

Hi Drew,

VREF is provided external VREF (REF3516).

The design is to supply external REF after AVDD is turned on, but it will be output momentarily due to a mistake.
We are investigating the impact on ADC3644.

+1 Drew Harrell over 1 year ago in reply to Hirotsugu Kobayashi

TI__Intellectual 2280 points

Hi,

Got it. The power supplies should be fine as is. Comparing the timing diagram and your scope image, I would suggest delaying the reset pulse to not go high until VREF is settled. As long as VREF is stable, the ADC will perform as expected.

Best regards,

Drew

0 Hirotsugu Kobayashi over 1 year ago in reply to Drew Harrell

Mastermind 9590 points

Hi Drew,

The reset signal is connected to the FPGA. The FPGA outputs a reset pulse after starting up, but is it necessary to keep the reset signal low until the power supply stabilizes?

Is there a problem with the sequence in the attached diagram?

Best regards,

+1 Drew Harrell over 1 year ago in reply to Hirotsugu Kobayashi

TI__Intellectual 2280 points

Hi.

As long as the RESET pulse width is at least 1 us this should not be a problem.

Best regards,

Drew

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ADC3644: Power Up Sequecnce