Hello！
In this paper, when SYNC is misaligned with the internal data rate clock, does the "misalignment" mean that the internal data rate clock and SYNC are not multiples of each other?
To synchronize the digital filter reset with the pulse of SYNC, is it the internal data rate clock or the frequency of DRDY?
If is the frequency of DRDY and is synchronized with SYNC, is the frequency of SYNC and the frequency of DRDY an integer multiple relationship?
Hi yifei Zhang,
If CLKIN = 8.192M OSR = 16384 data rate = 0.25kSPS but the 6144Hz signal is trigger on the SYNC pin of ADS131M08，can the ADC samples and converts at a 6144Hz freq？and how to configure and use it to achieve this.
Every time you pull the SYNC pin low, the ADC restarts the conversion process. See the section on Fast Startup Behavior (8.4.2) for more information about what to expect when the conversion process restarts. Specifically the last two paragraphs, which I have copied below
Therefore, the first two samples after the SYNC will not be valid data, so you should ignore them. The settling time is given in Table 8-3 as you mentioned. The Sinc1 filter is enabled by default if you select an OSR>1024, this is not something you have control over
As I mentioned in my last post:
The sampling frequency is determined by the ADC clock (CLKIN), the operating mode (High resolution, low power, or very-low power), and the OSR setting you choose.
You can work backward to figure out what the fCLKIN frequency should be. For example, let's assume you want an output data rate of 6144 SPS (that is 128 points per period for a 48 Hz line cycle frequency). And let's say you also want to use High Resolution (HR) mode and an OSR of 512. Then, fMOD = 6144 * 512 = 3.145728 MHz, and fCLKIN = 2*fMOD, so therefore fCLKIN = 6.291456 MHz
So you need to be able to change the fCLKIN frequency in order to implement coherent sampling.
-Bryan
