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ADC3683EVM: What practical or easy to implement alternatives are there to using the default external clocks on J9 and J7 on this EVM?

Nigel Berrie
Prodigy 35 points
Part Number: ADC3683EVM
Other Parts Discussed in Thread: TSW1418EVM, ADC3683, TSWDC155EVM

I am using the TSW1418EVM with the ADC3683EVM, and have discovered that I need two RFsignal generators (65MHz and 292.5MHz) to supply both Sampling clock on J4 of the ADC3683EVM, and the DCLKIN clockon J9 of the EVM... And maybe ideally another RF signal source to test its performance!?!

I don't have access to two RF signal generators at the moment (forget three!)...

Also, if I wanted to use this ADC in my product designs, I want to be using a PCB-based clock source!

I note from the very good support documents for the ADC3683EVM that there is a signal input connection alternative for DCLKIN_FPGA_P and DCLKIN_FPGA_N from the interface with the TSW1418EVM, and the option of FPGA_CLK or FPGA_REF_CLK as alternative onboard clock sources, again from the TSW1418EVM interface

There is also provision for a four-pin clock source package (Y1) for the sampling clock, but no alternative input other than the J4 interface for the LVDS clock (so I am hoping that the TSW1418EVM can supply that clock...?

Any comment on using these alternative clock sources?

Perhaps they are not implemented on the TSW1418EVM, or not properly debugged and therefore not advisable to use?

Any practical information appreciated.

I am perfectly capable of soldering and desoldering 0 ohm links, or other components to mould this ADC3683EVM PCBA to my needs if that is what I need to do, but it would be useful to know if that is not advisable.

I can find no blogs or accounts online of someone using these kits to evaluate the ADC3683, but would be very willing to construct one myself if I can get this going!

  • 0
    TI__Mastermind 37960 points

    Hi Nigel,

    We also don't have any FW available for you to capture data from the ADC3683 to the TSW1418.

    Who guided you to purchase the TSW1418?

    As for a clock source, to provide both the sampling clock and DCLKIN, we have some LMK/LMX clock solutions/EVMs that could be used.

    Give me a few days to to get you solution there or loop in the right person from our clocking group.

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 35 points

    Thank you for your support Rob, it is very much appreciated.

    I was guided by an answer to my previous question on this forum:

    https://e2e.ti.com/support/data-converters-group/data-converters/f/data-converters-forum/1335731/adc3683evm-what-are-now-the-best-tools-to-evaluate-this, which I posted because the TSW1400EVM is obsolete and generally no longer available.

    The TSW1418EVM was also marked as obsolete by Digikey (but not by others) but the person who kindly answered me (Geoff Roth) advised me that it wasn't so, and advised me to purchase it, so I also flagged that to Digikey...

    There does appear to be FW - I am using the HSDC Pro GUI version 6, and it has FW to drive the TSW1418EVM to control the ADC3683EVM in various modes and various sample rates or numbers of bits...

    I chose the option ADC3683_2CH_2W_18-bit... I think it was (not to hand at the moment as I am working from home today and the GUI doesn't offer anything unless it is connected to the TSW1418EVM!) - but I need to use it at 18-bit, dual-channel, 65MS/s for an application with bandwidth DC to ~7MHz where DC accuracy is important.

    So I may have to optimise the ADC3683EVM input bandwidth once I have got it going.

    But the HSDC Pro GUI complains that there is no ADC_SERIAL_CLK, and ADC Interface MMCM is not locked or ADC Clock is absent - and looking at the circuit diagram supplied with the ADC3683EVM I can see that the default hardware I have been issued takes the sample clock and LVDS databus clock from the sma connectors, not the TSW1418EVM interface... so it is not surprising that the clocks are absent! But also perhaps indicates that there is no FW in existence currently that will correctly drive those clock signals.

    If I can resolve this with some LMX clock solutions/EVMs that are off-the-shelf then that would be marvellous, thank you. I will need to get them pretty urgently, though, if I am to complete this evaluation in a timely manner!

    A pity about the apparently partial solution offered by the TSW1418EVM... not what I expected!

    I await your follow-up message(s) about that.

    Many Thanks for your prompt answers so far!

    Nigel Berrie

    Senior Design Engineer at PFO Instruments in the UK

  • 0 in reply to Nigel Berrie
    TI__Mastermind 37960 points

    Hi Nigel,

    Unfortunately, we don't have a solution where the FPGA clocks are exposed to provide the clock for the DCLKIN.

    Typically we ask customer to supply two independent 10MHz ref locked signal generators in order to sample correctly.

    This is not uncommon for RF ADCs where this is required as well.

    Let me dig into this more and see what we can provide you to get you going.

    Please give me a few more days on this.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    TI__Mastermind 37960 points

    Hi Nigel,

    I apologize for the delay.

    Please use the TSWDC155EVM instead of the TSW1418EVM.

    If you have already purchased the 1418EVM please let me know.

    Thanks,

    Rob