Hello,
We are using ADS1282 controlled by FPGA.. ADC CLK =4.096MHZ.
Powered ADC -> applied CLK -> release PWD pin -> release Reset Pin.
DRDY pin goes high and stays high;
Try to reconfigure ADC by sending 0x41, 0x0 0xD9
didnt help DRDY always stays high.
If there is anything we can check, change, to get DRDY pin to start toggle?
Thank you
Hello Iouri,
When the ADS1282 is first powered-up with a clock present, the DRDY pin should toggle at the output data rate. With CLK=4.096MHz, you should see a 1kHz rate on the DRDY pin.
Verify that you have proper signals on the ADC pins, including power and clock. Verify the /RESET, /PWDN, and SYNC pins are all driven high and not floating. Verify 5V on AVDD (assuming unipolar operation), DVDD has 2.25V to 3.3V, or 1.65V to 2.25V with BYPAS pin connected to DVDD. Also make sure the BYPAS pin has a 1uF connected to ground and should measure 1.8V when not connected to DVDD.
Regards,
Keith Nicholas
Precision ADC Applications
