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ADS1274EVM and McBSP (DSK6455)

Manuel Fernandez-Ros
Intellectual 880 points
Other Parts Discussed in Thread: ADS1274, TMS320C6455

Hello

I don't understand well the connection between ADS1274EVM and McBSP of a DSK6455. When SW12 is turned on the left (ADS1274EVM) I use SPI protocol, then the 27 MHz clock is connected to CLK (ADS1274) and CLKR (J5-McBSP), /DRDY (ADS1274) is connected to FSR (J5-McBSP) and SCLK (ADS1274) is connected to CLKX (J5-McBSP. Must McBSP generate the SCLK signal via J5-CLKX? Could you help me?

In the document SPRU580 (McBSP) page 18 the internal clock is CPU/6, is it right or CPU/4? My CPU is 6455.

Manuel Fernández Ros

Thanks.

Best regards.

  • 0
    TI__Guru**** 180741 points

    Hi Manuel,

    By default, the ADS1278EVM is setup for Frame Sync mode.  The SCLK and CLK source are actually from J5, pin 5 (the CLKR pin of the McBSP).  S12 is shown in the schematic for the EVM in its default(FS Mode) state.  Since we have no need to use the transmitter side of the McBSP port, we are using the receiver only, with CLK and SCLK sourced by the DSP via CLKr.  In Frame Sync mode, the FS input of the ADS1274 is connected to the FSr output so that the ADC knows where each new frame starts.  Please also note that there is a DFF on the board which delays the MSB so that it is valid on the first clock after the FS pulse.  I believe your TMS320C6455 is using CPU/6 (by note 7 on page 190 of the TMS320C6455 data sheet).

  • 0 in reply to Tom Hendrick
    Intellectual 880 points

    Hello Tom,

     

    Sorry, but I have a doubt in your answer: /DDRY-FSYNC (ADS1274 in mode FS)  is input or output? And FSR (McBSP) for mode FS, is output or input?

    Thanks

    Best regards.

  • 0 in reply to Manuel Fernandez-Ros
    TI__Guru**** 180741 points

    Sorry for the confusion Manuel,

    In Frame Sync mode, the FS pin on the ADS1274 is an input and the FSr is an output driving that pin.