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DAC12DL3200: DAC not updating from LVDS

Joel Brinton1
Prodigy 20 points
Part Number: DAC12DL3200

Hello,

We are using the DAC12DL3200 in a radio transmitter application and are having trouble configuring it. We can use the SPIDAC register to update the output, but when configured for LVDS we get no change in output (except by changing the SPI coarse gain control). Can you please review our register settings and let us know what we may be doing wrong? The datasheet is a little ambiguous on the configuration details.

thank you,
joel

p.s. we were asked by our FAE to post this in the processor forum

const uint32_t DAC_REGS[5] =  {

  0x101f1,

  0x16033,

  0x17000,

  0x10000,

  0x2203,

  0x18000,

};



0000313298-B01-R1.RC4-schematics(dac_no_titleblock).pdf

  • 0
    TI__Expert 6150 points

    Hello Joel,

    In your first line of register writes I am assuming you are changing the value to enable LVDS mode of the DAC, in its current configuration it seems like you are writing 0xF1 to register 0x101 which would set both DACs to the SPIDAC setting.

    Also have you had a chance to look at section 8.1.1 of the datasheet? It details the startup procedure for the DAC in LVDS mode.

    Best,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 20 points

    Hi Eric,

    Thank you for your reply. Sorry for my slow response I've been out sick. We actually set 0x101 to 0x51, we were just using 0xf1 to test SPIDAC mode. Apologies for not reverting the code before commenting. Here's my notes on our LVDS startup. Using 8.1.1:

    1. Start the DEVCLK : there's nothing in the documentation that defines what DEVCLK is, so we're assuming this means CLK (pins A15, A14). Confirm?

    2. Apply power per the order in the power sequence section : here's what the DS says about sequencing... "supplies... can be applied in any order as long as the cumulative time in a state where only some supplies are active is less than one year." that looks like a typo or a placeholder. We're currently bring up supplies at the same time.

    3. Assert Reset :datasheet says at least 25ns. we do about 10ms. Confirm?

    4. De-assert Reset

    5. Program part configuration : see DAC_REGS above. These program fine and read back fine.

    6. Wait for FUSE_DONE=1

    7. Apply LVDS signals (and SYSREF if used) to inputs. This may have been done at any earlier point if desired, but must be stable by here

    8. Set DP_EN=1

    9. Clear LVDS_CLK_ALM & STROBE_ALM : note LVDS_CLK_ALM was asserted before clear

    10. Synchronize the system : we use LVDS strobes for alignment. Do we assert strobe on every frame or is it only used once? Is it active high or active low?

    11. Configure FIFO_DLY

    12. Clear all SYS_ALM bits : note no SYS_ALM bits are asserted by this step

    13. Wait 100 DACCLK

    14. Enable transmission : TXEN is already asserted by this point (pin tied LOW per eval board). Do we need to deassert it before beginning this section?

    Can you reply to my questions above?

    thank you,

    joel