ADS9813: behavioral models to simulate digital interface for FPGA IP development?

Team,
I saw that we provide IBIS model for ADS981x on TI.COM.

But do we have some behavioral models (like Verilog or VHDL) for the ADS981x digital interface that we can share?
This is to help for FPGA side IP development to interface to ADS981x.

I know that we provide JESD IP for some of our HS ADC:
https://www.ti.com/tool/TI-JESD204-IP
Do we have plan to include other TI interfaces too?

Thanks in advance,

Ant