ADC3683: Jitter on DCLKIN

Dear TI Team,

in the datasheet it is written that Jitter on DCLKIN must not be higher than +/-50ps. In our design the ADC sampling clock and the DCLKIN clock will be frequency-aligned driven by FPGA. However, compliance to the +/-50ps jitter specification is very challenging if driving the DCKLIN clock from FPGA. The ADC sampling clock is 10MHz in our design and we will use 1-wire LVDS output (16-bits) with 80MHz DCLKIN.

For better understanding we have following questions:
- How is the +/-50ps jitter specified (rms or peak-to-peak)?
- In the datasheet it is stated that the specifeid DCLKIN jitter is the max value allowed and does not scale with sample rates. Can you explain why the DCLKIN jitter does not scale with sample rates?
- Does the jitter value scale with DCLKIN frequency?
- From technical point of view, could you please provide a functional description how DCLKIN clock signal is used on-chip and why jitter is so important? How is the data transfer from ADC sampling clock domian to DCLKIN clock domain implemented?
- Is there a functional block diagram availiable which describes the on-chip CLOCK architecture and imlpementation (CLK sampling clock, DCLKIN, DCLK, FCLK). How are the clocks derived and related to each other?
- Could you please explain what happens if a DCLKIN signal with jitter of approx. 150ps...200ps rms will be applied?

Thank you very much in advance!