ADS8689: CONVST/CS and SCLK are LOW when RST low-to-high transition?

Hi Experts,

Good day.

Paragraph 7.4.2.1. RESET state

"In order to exit any of the RESET states, the RST pin must be pulled high with CONVST/CS and SCLK held low.
After a delay of tD_RST_POR or tD_RST_APP (see the Timing Requirements: Asynchronous Reset table), the device
enters ACQ state and the RVS pin goes high"

Does this mean that CONVST/CS and SCLK must be held low during the RST low-high transition, or does the ADS8689 leave the RESET state the at the earliest occasion when /RST high, /CS low and SCLK low applies concurrently?

Thank you for your assistance.

Regards,
Archie A.