Hello There,
I have a question about setting up the ADS54J60 with a LMFS value of 4244, JSED204B LineRate = 5Gbps. Is it possible to get an ADC sampling rate of 384MSPS when the input clock is 384MHz (divided by 1). When I set the PLL_MODE to 40X, the JSED fails to establish a link. But when I set the PLL_MODE to 20X, the link is made, but the output signal seems to be sampled at 192MSPS, as if it's always divided by 2. I have observed that when using a clock signal of 384MHz, the registers at memory address 6900h always show a value of zero, but when using a clock signal of 768MHz (Output signal is sampled at 384Mhz), the registers are set correctly. Do you have any advice about this behavior.
For the LMK setup i have the following
1- Disabling PLL1 and PLL2
2- CLKin1 --> Fin
3- VCO_MUX --> CLKin1 (External VCO)
* Divider value for DCLKout0 (FPGA JESD Core Clock) = 4
* Divider value for DCLKout2 (ADC 3 & ADC 4 Clock) = 1
* Divider value for DCLKout4 (ADC 1 & ADC 2 Clock) = 1
* Divider value for DCLKout6 (FPGA ADC Module Clock) = 4
* Divider value for DCLKout8 (FPGA DAC Module Clock) = 4
* Divider value for DCLKout10 (DAC 3 & DAC 4 Clock) = 2
* Divider value for DCLKout12 (DAC 1 & DAC 2 Clock) = 2
Divider value for SDCLKout1-11 (SYSREF Clocks for all DCLKoutx signals) =128 from SYSREF = LMFC((fs / 4) / K) / 2^N
ADS54J60
MAIN DIGITAL PAGE (JESD BANK PAGE SEL = 6800h)
- Reg_41 = DECFIL_DISABLE = 0x0
-Reg_4D = DECFIL_MODE_DISABLE =0x0
-Reg_52 = DEC_LANE_DISABLE= 0x0
-Reg_72 = DEC_LANE1_DISABLE= 0x0
JESD ANALOG PAGE (JESD BANK PAGE SEL = 6A00h)
-Reg_16 =PLL_MODE_40X =0x2
- PLL Reset
JESD DIGITAL PAGE (JESD BANK PAGE SEL = 6900h)
-Reg_0 =CTRL_K_ENABLE=0x80
-Reg_1 = JESD_FILMODE_BYPASS/JESD_MODE_40X_2LANE =0x2
-Reg_5 =SCRAMBLE_DISABLE
K=16
-Reg_7 =JESD204B_SUBCLASS1 =0x8
-Reg_16 = LANE_SHARE_DISABLE =0x80
MAIN DIGITAL PAGE (JESD BANK PAGE SEL = 6800h)
-Reg_0 PULSE RESET
