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Original question:

ADS8686S: Programmable LPF Questions

ADS8686S: Bandwidth using Oversampling

Cornelius Fink
Prodigy 65 points
Part Number: ADS8686S

Dear TI-Team,

we want to use all channels of the ADC in Hardware Mode and OSR=32. Therefore we consider a sampling rate for each of the channels of 3.90625kHz.

According Table 7-3 of the datasheet, the -3dB bandwidth in this mode is 12.9kHz. 

Is the assumption correct, that this cut-off frequency of 12.9kHz needs to be divided by "8" (resulting in ~1.6kHz) to have the cut-off frequency per channel?

Otherwise the sampling rate per channel and the defined -3dB bandwidth frequency would not match.

Thank you for your feedback!

  • 0
    TI__Mastermind 45435 points

    Hi ,

    When you sweep input channels on the multiplexer and convert signals on the ADS8686S ADC, the sampling per channel is equal to 1Msps/8=125ksps, however the internal digital filter is an additional function to average the data in order to reduce the noise and improve the SNR of the ADC after the ADC completes individual data conversion, the internal digital filter requires additional time because it averages multiple samples according to the OSR configuration which determines the bandwidth of the digital filter, this function is different from the ADC's data conversion, so it should not be considered as a divided bandwidth per channel.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 65 points

    Hi Dale,

    thank you for your fast reply.

    Does it mean, that the OSR filter (2nd order)  does not contribute to the needed anti-aliasing filter? Because the resulting sampling frequency (from a "host" point of view) is then e.g. 125/32= ~3.9kHz, where I would expect a lowpass filter at a frequency of ~3.9kHz/2 = ~1.8kHz. The -3dB bandwidth of the OSR filter (12.9kHz) is far off...

    Best Regards, Cornelius

  • 0 in reply to Cornelius Fink
    TI__Mastermind 45435 points

    Hi ,

    I will get it back to you tomorrow, thanks.

    BR,

    Dale

  • 0 in reply to Dale Li
    TI__Mastermind 45435 points

    Hi Cornelius,

    The speed of data stream to the digital filter inside the ADS8686S ADC is always 1Msps (sampling rate) whether the internal multiplexer is switching or not, so your sampling rate should not be divided by the number of channels (e.g. 1Msps/8=125ksps) in your calculation. I did the following calculation and analysis for you:

    As you can see from the analysis table above, the output date rate (ODR) are calculated based on the acquisition time and conversion time under different OSR configurations, these are the actual data speed shifted out by the ADC and can be seen by your microcontroller. The bandwidth (BW) of digital filter can be calculated with ODR/(1+the order of filter) as a common approach, the order of the SINC filter in ADS8688S is 2,so the BW for every OSR configuration can be calculated as shown in the table above. I also listed the BW of the internal analog LPF in ADS8686S,  so the yellow boxes in the table show the dominated BW of the whole signal chain under the specified OSR configuration. As you can see, the dominated BW in yellow match the specified BW of the digital filter in blue which are shown in the table 7-3 in ADS8686S datasheet.

    I hope my calculation and explanation can help you understand well.

    Best regards,

    Dale Li

  • 0 in reply to Dale Li
    Prodigy 65 points

    Hi Dale,

    I'm sorry, but I do not understand your reply.

    According to the datasheet description of the hardware burst sequencer, each input is sampled n-times (depending on the OSR settings). Afterwards, the next input is captured. 

    Therefore I would definetly expect, that the real effective sampling rate for each individual input (seen by MCU via SPI) is calculated by 1 MSPS divided by nb of input channels devided by OSR. So in our Use-Case (hardware mode, burst-sequencer) it is 1 MSPS / 8 input channels / OSR=32 results in 3.90625kHz (for each of the input channels). Considering this calculation, an anti-aliasing filter is needed with a cut-off frequency in the range of ~2kHz. 

    Seeing your table above, it seems that the digital filter cannot be taken into account, since its bandwidth is more in the range of 12kHz.

    In other words, the hardware needs to consider the OSR setting, and it cannot be dynamically changed, since the filter(s) provided by the ADC cannot be used as anti-aliasing filters.

    Best Regards,

    Cornelius

  • 0 in reply to Cornelius Fink
    TI__Mastermind 45435 points

    Hi Cornelius,

    I do not have the details to show you how the internal digital filter was designed, but unfortunately there is nothing we can change on the existing silicon.

    BR,

    Dale

  • 0 in reply to Dale Li
    Prodigy 65 points

    ok, thank you!