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ADC12DJ5200RFEVM: Diagrams in ADCxxDJxx00RF Evaluation Module User's Guide

Part Number: ADC12DJ5200RFEVM
Other Parts Discussed in Thread: LMK04828, LMX2594, LMK61E2, LMK00304

I have some questions about ADCxxDJxx00RF Evaluation Module User's Guide (Rev. B)
User Guide URL: https://www.ti.com/jp/lit/ug/slau640b/slau640b.pdf?ts=1716456114996&ref_url=https%253A%252F%252Fwww.ti.com%252Ftool%252Fja-jp%252FADC12DJ5200RFEVM

Q1. I consider that the SYNC signal input from the LMK04828 to the LMX2594 is used to align the output signals of multiple LMX2594 devices. (Fig7-2)
In the EVM diagram, there is only one LMX2594, so there is no need to input the SYNC signal, right?

Q2. When using the Onboard Clocking System(Fig 7-2), the SYNC signal and SYSREFREQ signal are input from LMK04828 to LMX2594.
But, why are the SYNC and REFSYSREQ signals not input in the External Reference Clocking System(Fig 7-3)?

Q3. Why does the origin of SYSREF change just by changing the input source?

Q4. I believe that the LMX2594 outputs RFOUTA and RFOUTB need to be synchronized.
The External Reference Clocking System is satisfied because RFOUTA and RFOUTB are generated from OSCIN.
How does Onboard Clocking System synchronize?

Q5. What is Board SYNC?
Is it different from the SYNC~ sent from the RX side of JESD204?

  • Hello Makoto,

    Q1. Yes this is correct.

    Q2. They are not enabled by default as it is not a requirement because all clocks are derived from a single source in both cases actually and do not have to be synchronized.

    Q3. The signal you highlight is not a sysref signal it is the reference clock for all the other clocks to be derived from. In on board clocking mode it comes from a clock synthesizer LMK61E2, in external reference mode it comes from an external signal generator.

    Q4. I don't understand this question in both modes of operation the reference clock for the LMX2594 is derived from oscin of the LMK00304, all this chip does is buffer the input clock to both the LMK04828 and LMX2594.

    Q5. This is an external JESD sync that can be used for debug, but by default you should use sync from the FPGA for operating the JESD link.

    best,

    Eric

  • Thank you for your reply.
    I don't think the question I asked came across correctly to you.
    I will revise the wording of the questions (Q2, Q3, Q4).

    I understand about Q1 and Q5. Thank you.

    Q2. 

    In Onboard Clocking System, SYNC and SYSREFREQ signals are input from LMK04828 to LMX2594.
    When in External Reference Clocking System, SYNC and SYSREFREQ signals are not input from LMK04828 to LMX2594.
    In fact, as answered in Q1, the SYNC signal is not needed in either clocking system.
    What is the reason why the SYSREFREQ signal is not input from LMK04828 to LMX2594 when External Reference clocking system is used?

    Q3. 

    When the Onboard Clocking System is used, SYSREF is generated based on the SYSREFREQ received from LMK04828.
    When the External Reference Clocking System is used, SYSREF is generated based on OSCIN (LMX2594 input).
    Why does the source signal for SYSREF generation change when the Clocking System is different?

    Q4. 

    When using the External Reference Clocking System, RFOUTA and RFOUTB are synchronized.
    Because it generates RFOUTA and RFOUTB from a single OSCIN input.
    However, when using the Onboard Clocking System, RFOUTA and RFOUTB are not synchronized.
    This is because RFOUTA is generated from OSCIN and RFOUTB is generated from SYSREFREQ, so the signal sources are separate.
    Q4-1. Do RFOUTA and RFOUTB need to be synchronized?
    Q4-2. If the answer to Q4-1 is yes, how do you synchronize RFOUTA and RFOUTB?

  • Hello Makoto,

    Q2. In both cases sysref and sync are not used they are by default powered down from the LMK04828 to LMX2594.

    Q3. The diagram here is misleading, the default state of the evm is for sysref to always be generated from the lmk to the ADC and FPGA. There is also support for sysref to be generated from the LMX to the ADC and bypassed from the lmk through the lmx to the ADC. But this would be un necessary. 

    Q4. This is not true, RFOUTA and RFOUTB are by default generated from the lmx2594 in both these modes, so they are synchorinzed.

    Can you give some more details on exactly what your use case is, the evm is meant for broad and quick evaluation purposes and might not be the best design for all systems and use cases.

    Thanks,

    Eric

  • For example, there is a use case as shown in the figure below.

    I have reflected your answers in the figure.

    Is this diagram correct?

    If we want to discuss more details, is it possible to have a closed discussion (not on the TI forum)?

  • Hello Makoto,

    Yes the diagram looks fine, I am still trying to understand exactly what features you are looking for? 

    Is the requirement just on board clocking of the ADC or something more complicated?

    Thanks,

    Eric

  • I would like to use both the Onboard Clocking System (which generates the input clock from the LMK61E2) and the External Reference Clocking System (which uses an external clock).
    I want to change the clock source statically using JumperPin. (Not dynamic.)
    As I asked in Q2 to Q4, ADC EVM User Guide describes different SYNC and SYSREFREQ paths for each Clocking System, so I don't know how to design my system where both onboard and external reference clocking system coexist (especially a clock system using LMK and LMX).

  • Hi, Eric

    This is just a friendly reminder that I’m waiting for your reply.

    If you need more information, let me know.

    I will provide you with as much information as possible.

    Best regards,

    Makoto

  • Hello Makoto,

    Apologies for the delay, I think the simplest thing to do would be to configure the part using the configurations modes in the ADC GUI and then you can modify the clocks to ensure the sysref always comes from the same source. My recommendation would be to ensure that sysref always comes from the LMK to all the other devices on the board.

    Best,

    Eric

  • Hi, Eric

    Thank you for your all replies.

    In both Onboard and External cases, I would design SYSREF to be generated from LMK and distributed to ADC and FPGA (as shown in the use case diagram).

    Best regards,

    Makoto