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ADC12DJ5200RF: JESD204C AND SERIALIZER LATENCY from ADC12DJ5200RF Datasheet

Ziquan Qin
Prodigy 30 points
Part Number: ADC12DJ5200RF

Tool/software:

The figure upper is from ADC12DJ5200RF datasheet(P30, 6.10).With about the tTx,in my opinion the non-deterministic delays(b) is the delay from  TxLMFC to JESD204 serail output.And the deterministic delays(a) is the fixed delay from SYSREF to TxLMFC.How can I know the deterministic(a)?OR I can use it as same as the  the fixed delay(c)  in FPGA from SYSREF to RxLMFC .

The figure below URL: https://ez.analog.com/cfs-file/__key/telligent-evolution-components-attachments/00-423-01-00-00-19-60-57/pg066_2D00_jesd204.pdf

  • 0
    TI__Expert 6150 points

    Hello Ziquan,

    I am a little bit confused what you are trying to accomplish can you please clarify your question a bit. The deterministic latency is of a JESD system is found by finding your worst case delay for a given system and then setting your release buffer delay value on your receiver to ensure that you never violate this delay.

    Best,

    Eric

  • 0 in reply to Eric Kleckner
    Prodigy 30 points

    Hello Eric,

    I'm sorry I didn't clarify my question.I want to know that in this sentence" The value given for tTx include deterministic and non-deterministic Delays",what does this deterministic delay and non-deterministic delay refer to?

    And how can I know the range of non-deterministic delay and What is the exact value of this deterministic delay？

    Waiting for your answer.

    Qin

  • 0 in reply to Ziquan Qin
    TI__Expert 6150 points

    Hello Ziquan,

    "what does this deterministic delay and non-deterministic delay refer to?"  This means that some delays will be deterministic (value is know and will stay constant) non deterministic means some delay will change over process, temperature and voltage as stated in the datasheet.

    The range is shown in the picture you screenshotted, it specs the total delay for t_tx, deterministic + non deterministic.

    best,

    Eric