TI-JESD204-IP: TI JESD204C IP simulation issue

David Caruth

Part Number: TI-JESD204-IP

Tool/software:

Hello,

I'm trying to run a simulation in Vivado with the TI JESD204C IP TX and RX cores back-to-back and am seeing that the rx_all_lanes_locked signal out of the RX core (as well as TX) is always 'Z'. I am following the recommended reset procedure and have checked that I'm not doing something dumb with signal assignments. Can you think of anything that would be causing this issue?

Thanks!

7 months ago

0 David Chaparro 7 months ago

TI__Genius 14991 points

Hi David,

Is this simulation for 8b10b or 64b66b encoding? If 8b10b, was the SYNC signal also looped back?

Regards,

David Chaparro

+1 David Caruth 7 months ago

Prodigy 60 points

Hi David,

I figured out what I was doing wrong. I had IP_TYPE set to "TX" in the .vh file. When I set it to "TXRX", I was able to simulate the TX back-to-back with the RX. This was 64b66b, to answer your question.

Thanks,

Dave

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TI-JESD204-IP: TI JESD204C IP simulation issue