• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 47 subscribers
  • Views 196 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ADS127L11: Daisy-chain synchronization

Jonas Martin
Prodigy 30 points
Part Number: ADS127L11

Tool/software:

Hello

I am designing a pcb where I want to connect 2 ADS127L11 in daisy-chain mode.

I am looking at ADS127L11 in Simultaneous-Sampling Systems and the TIDA-010249.

In the Simultanoues Sampling Documen ADC clock is inverted in the start/sync synchronziation circuit. Which makes sense as we want the Flip Flops to trigger on the falling edge of the clock, to get rid of the 1 cycle uncertainty.

However in the schematics of the reference design, no such inversion takes place.

Am I missing something? Or is there an error in the Reference design?

And why are 2 D-Flip-Flops used at all? Wouldn't 1 suffice?

Thanks for your help

  • 0
    TI__Mastermind 41161 points

    Hi Jonas Martin,

    Today is a holiday in the US, we will respond to your post later this week. Thanks for your patience

    -Bryan

  • +1 in reply to Bryan Lizon86
    TI__Mastermind 40640 points

    Hello Jonas,

    Good catch, this is an error.  However, worst case, the 4x ADS127L11's will be out of sync by 1 CLK period.  I do not think we noticed this on the reference design since the SYNC signal is already synchronized to the CLK signal (the FPGA on the PHI controller card uses the 16MHz CLK oscillator for timing).

    The dual flip-flops increase the odds that the output will be fully stable, since a single stage flip-flop can have a small period of meta-stability depending on the timing of the input transition and the clock.  This suggested circuit is a rule of thumb for digital synchronization between two clock domains, and depending on the exact characteristics of the logic you are using, a single stage flip-flop may be adequate.

    Also note that the flip-flop is not needed as long as the timing shown in Figure 6-4 of the datasheet can be met, which is typically the case when the host processor/FPGA uses the same clock source used for the ADC.

    Regards,
    Keith Nicholas
    Precision ADC Applications

  • 0 in reply to Keith Nicholas
    Prodigy 30 points

    Hi Keith

    Thanks for the reply. This cleared things up.

    I will probably not need any flip flops. Due to both the Microcontroller and the ADCs beeing connected to the same clock source.

    And additionally being out of sync by 1 clock cycle shouldn't even be  problem for me

    Regards,

    Jonas