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DAC63204EVM: Getting Negative Currents from the DAC in a typical setup includign the EVM

Matthew Gibson
Prodigy 10 points
Part Number: DAC63204EVM

Tool/software:

Hi,

On the DAC63204EVM Data sheet it references getting negative current from the device. Does this require a negative voltage input to AGND? Or is there some type of configuration that can allow it by powering VDD with 5V and AGND with GND = 0V? If anyone can help with the correct configuration would appreciate it.

Additionally, the NVM won't save the configuration after I power the device up again, after being in the GUI. Is there a way to save the setting like automatically keeping hte DAC IOUT running at whatever waveform i set? Because the Program NVM Button on the GUI doesn't seem to work.

Thanks!

Matt

  • 0
    TI__Mastermind 41903 points

    Hi Matt, 

    No, there is no negative voltage required for the negative IDAC current. VDD should be in the 1.8V to 5.5V range, and AGNF should be 0V. 

    There is a bug in the DAC63204EVM-GUI. You can either switch to the more updated SMART-DAC-EVM-GUI, or on the DAC63204EVM-GUI and directly write to the NVM-PROG bit in the COMMON-TRIGGER register (write 0x0002 to register 0x20). 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    Prodigy 10 points

    Hi Katlynne,

    Thanks for your response! I will switch GUIs.

    For the first response, I tried using the DAC63204EVM GUI to generate the negative currents, but it could only perform the positive currents. To achieve a negative current does the DAC IOUT line have to be connected to an above ground voltage? I can't see how the setup can generate a negative current or if im missing something in the datasheet pls let me know about the setup and what the IOUT line should be connected to directly. Thanks!

    Matt

  • +1 in reply to Matthew Gibson
    TI__Mastermind 41903 points

    Hi Matt, 

    The GUI will be able to configure both the positive and negative current. You're right, the IOUT pin would need to be greater than 0V for the device to be able to sink the IOUT current to ground. The compliance voltage of the IOUT pins is 400mV from AVDD (if sourcing current @ full-scale) or above GND (if sinking current @ negative full-scale):

    This plot demonstrates the requirement a bit better. You can see that if you are not providing enough output headroom (from GND or AVDD) then the device will not be able to drive the configured output current. The headroom requirement is less than 400mV if you are not operating at full-scale. 

    Best,

    Katlynne Jones

  • 0 in reply to Katlynne Jones
    Prodigy 10 points

    Thanks so much Katlynne, that helps a lot! I appreciate your quick and awesome responses!

  • 0 in reply to Matthew Gibson
    TI__Mastermind 41903 points

    Hi Matt, 

    Great to hear, please let me know if you end up having more questions. 

    Best,

    Katlynne Jones