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ADC12QJ1600: ADC12QJ1600

Giora Eytan
Expert 1265 points
Part Number: ADC12QJ1600

Tool/software:

Hello,

In our design we route 8 ADC12QJ1600 to FMC and FMC+ connectors connected to an MPSOC FPGA.

Questions regarding the JESD204 IP :

1. Can I map the ADC Lane0 to Lane3 (JMODE8 used) to the FPGA Quad serdes RX0 to RX3, so that Lane0 will be connected to RX3 and so on?

2. Can I map the ADC lanes _P to FPGA RX _N and Lane _N to FPGA RX _P? i.e. cross the _P and _N connection..

3. Where do I state the physical mapping of the ADC Lanes to FPGA Serdes Channels in the JESD204 IP we got from TI?

Thanks for the quick response 

Giora 

  • 0
    TI__Expert 6150 points

    Hello Giora,

    Yes it is possible to map any ADC lane to any FPGA lane as well as invert the lanes from the adc to the FPGA, all of this is taken care of by the TI JESD IP. Are you able to share some details about how you are using the TI JESD IP, mainly are you working with a custom reference design or just the IP core?

    Thank you,

    Eric

  • 0 in reply to Eric Kleckner
    Expert 1265 points

    Eric hi 

    Yes I can share any data you require

    I have to be sure before going to production with the PCB that no mistakes in this area will occur.

    We are using the TI JESD IP and NOT custom reference. 

    I saw that in the IP directory the "jesd_link_params.vh" configures all of the above. 

    Just need solid confirmation. 

    Thanks in advance 

  • 0 in reply to Giora Eytan
    TI__Expert 6150 points

    Hello Giora,

    I see typically we provide custom reference designs to work with the IP to simply things and help expedite your design.

    If you can give me the following info I can make a custom design for you that will work for your intended mode of operation.

    Desired JMODE: I think this is 8 based on your previous question

    Desired FPGA dev kit: Is it a TI capture card or a standard Xilinx Dev kit.

    Best,

    Eric

  • 0 in reply to Eric Kleckner
    Expert 1265 points

    Hello Eric,

    We have come to an issue with the implementation of the 8 ADC12JQ1600 connecting to XCZU19EG-1FFVC1760 on our sub contractor side. 

    It would be very helpful if you can review the pin mapping (ADC to FPGA(GTH/GTY)) and let us know it is feasible. 

    We wish to work in JMODE8 (i.e. 64/66 4 lanes max rate 12.375gbps = Max. sampling frequency of 1Ghz @ 12bit). 

    The very best for us, will be sending us a custom TI IP for our intended board connections. 

    Please see attached XLS spreadsheet with the channels to lane mapping.

    Once again this is NOT an AMD/Xilinx EVK but a 3rd party (iWave) SOM and we interface to their EVK FMC and FMC+ connectors. 

    In general any recommendations/suggestion would be highly appreciated. 

    Thanks in advance

     MakaluOptic_ADC12JQ1600_SIGNAL_MAPPING.xlsx

  • 0 in reply to Giora Eytan
    TI__Expert 6150 points

    Hello Giora,

    This sounds a little complex I will reach out to you offline to follow up. 

    Thanks,

    Eric