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The ADS1299 uses a delta-sigma ADC topology. Therefore, the ADC output is the result of many delta-sigma modulator samples, which are averaged and decimated. The falling edge of nDRDY indicates when the output conversion result is loaded into the SPI shift register and available to read.
The first conversion result requires additional settling time delay due to the architecture of the sinc-3 digital filter. After the first result, all ADC output samples will be available at the data rate period (1 / fDATA).
