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ADC31JB68: ADC31JB68RTA25 vs. ADC31JB68RTAT

Ralf Rascher
Prodigy 25 points
Part Number: ADC31JB68
Other Parts Discussed in Thread: LMK04821

Tool/software:

Hi,

a few years ago we build a data acquisition board with 4 x ADC31JB68RTA25 connected to an Xilinx Artix.

The ADCs are clocked with 400 MHz. The Xilinx FPGA filters the data and sends them to a PC over Ethernet.

We got the board working, with the help from an TI engineer, who told us to set a undocumented bit

in an register.

We now build more boards, however, as that part is not available anymore we used 4 x ADC31JB68RTAT.

The new boards seem to sample data, however the received data on the PC look different, as if the sample

rate is not the same.

We suspect there might be a difference between the ...RTA25 and the ...RTAT version. Switching the ADC into

testmode to generate a ramp between 0x000 to 0xffff works. I cannot see any notes int the datasheet, regarding

the RTA25 and RTAT version. What is the difference between the two versions?

Cheers,

Ralf

  • 0
    TI__Expert 5430 points

    Hi Ralf,

    There is no difference between the two version, it's was just the the packaging qty, the RTA25 denoting a packing qty of 25.  Please see the datasheet snippet below to see the difference.

    Regards,

    Geoff

  • 0
    Prodigy 25 points

    Hi Geoff,

    thanks for clarifying.

    As our boards still don't work, I looked at the device markings. They are difficult to read,

    however the working boards looks like: 85AFC2G3, the non working: 8CA249G3.

    Reading out the Chip-Type, Chip-ID and Chip-Version, shows no difference.

    Probing all the relevant external signals like clocks, sync etc. are fine.

    The power supply is up and stable.

    Regards,

    Ralf

  • 0 in reply to Ralf Rascher
    TI__Mastermind 38150 points

    Hi Ralf,

    Can you please forward some "good" and "bad" data while we work on this?

    This might help clarify the issue as well.

    Are you sure nothing else has changed in the system board for example?

    Thanks,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 25 points

    Hi Rob,

    what "good" or "bad" data would you need? As I already wrote setting

    the ADC into test mode by programming the JESD_CTRL2 register to

    generate a ramp works perfectly and we can see the valid data inside the FPGA.

    However in normal data acquisition mode (applying a 10 MHz sine), the data are

    not what we expect.

    Yes, the system changed a bit, we did a new revision of the board

    to add a few signals to the FPGA, which are completely unrelated

    to the ADCs digital or analogue path.

  • 0 in reply to Ralf Rascher
    TI__Mastermind 38150 points

    Hi Ralf,

    if you are collecting data and have an expectation, this would be in the form of time domain or frequency domain.

    We are accustomed to looking at output data in order to determine what the problem might be.

    So for example, if you have a 10MHz FFT plot of what you expect and now an FFT plot of the 10MHz output of what isn't expected.

    Regards,

    Rob

  • 0 in reply to Rob Reeder
    Prodigy 25 points

    Hi Rob,

    we got it working. It was the clock generation chip, which provided the main clocks for the ADC and the FPGA.

    We use a LMK04821. We read out the regitsters for the lock bits, they were sets, but the clock signal had a huge jitter.

    We found two capacitors for the external loop filter at PLL2 were swapped. After correcting the loop filter, we had a

    stable clock and the data from the ADC were consistant.

    Regards,

    Ralf