ADS7843: Some questions

Some Replies:

1. In FIGURE 5 on page 8 of the data sheet, is it correct to assume that the BUSY pulse width is equivalent to one DCLK period based on the contents of FIGURE 7 on page 10?

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If in Power Down Mode, the BUSY pin shall remain High till the Next Falling edge of DCLK is received. If the clocks have not been stopped then this shall come in one DCLK Period. If Clocks are removed BUSY remains high till next DCLK falling edge occurs

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2. If ① is correct, is it correct to understand that the DOUT data output is output immediately after the BUSY output changes to LOW?

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Yes correct

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3. In FIGURE 5 on page 8 of the data sheet, is the DOUT output the data captured at the timing of tACQ just before that?

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At the end of tacq the acquisition of the analog sample is complete .

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4. According to TABLE IV on page 9 of the data sheet, if MODE is set to "1" (8bit Conversion), is it correct to understand that bits 3 to 0 of DOUT output "0"?

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Bit 7 comes first and then rest of bits down to 0.

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5. If IN3 and IN4 are not used, is it okay to connect them to AGND?

Yes.