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ADC32RF55EVM: Input power split

Part Number: ADC32RF55EVM

Tool/software:

Hello team,

My customer is planning to use INA1P, INA1M, INA2P, INA2M.

Is the input signal level divided equally on the EVM layout?
Is there any data for errors between each input pins? (Such as ±0.5dB)

Best Regards,
Kei Kuwahara

  • Hi Kei-san,

    The EVM split network is not through any power divider but the layout is evenly matched in time and impedance within each INAx, BINx input pair. I don’t think we have any data from EVMs about the mismatch between channels A1 and A2 or B1 and B2.

    Thanks, Chase