ADS5474 Timing

Timothy Starr

Other Parts Discussed in Thread: ADS5474, ADS54RF63, ADS5463, ADS5400

We ae considering the best way to sychronize several ADS5474 devices for simultaneous sampling at 400Msps. The ADCs feed an FPGA as whon in the attached document. One option is to use DDR signal DRY to clock in the DATA to the FPGA, however, according to the timing specifications in the sta sheet, the skew between DRY and DATA can be anywhere from +500 ps to -500ps. So, assuming the traces are all the same length, the setup time could be as low as -500ps and the hold time could be as low as -500 ps. How is this supposed to work? Is the only solution to delay the DRY using longer traces by1/2 clock cycle? Thanks and Best Regards,

-Tim Starr on behalf of MD@BD

ADS5474 timing 093011.pptx

over 14 years ago

0 KW Nam over 14 years ago

TI__Expert 8895 points

Hello,

First of all, option 2 utilizing DRY is not a good choice for multiple ADC operation because DRY in ADS5474 is not triggered by reset. Therefore you cannot use DRY for multiple ADC synchronization. Option 1 looks a good choice but you have to consider clock delay from your clock generator. ADS5474 datasheet specifies the propagation delay 800~2000ps. I’d recommend you set clock delay 1400ps because this is the center of delay between min and max propagation.

From 27-page of datasheet shown as below, it also points out the need to delay either DRY or DATA to meet setup and hold time into the FPGA. You pointed out one possibility to delay DRY with longer circuit board traces. The more common approach is to use the input cells available in the FPGA to adjust the timing into the IDDR cells, either IDELAY in the Xilinx or a PLL in the Altera.

“The values given for timing (see Figure 1) were obtained with a measured 10-pF parasitic board capacitance to ground on each LVDS line (or 5-pF differential parasitic capacitance). When setting the time relationship between DRY and DATA at the receiving device, it is generally recommended that setup time be maximized, but this partially depends on the setup and hold times of the device receiving the digital data (like an FPGA or Field Programmable Field Array). Since DRY and DATA are coincident, it will likely be necessary to delay either DRY or DATA such that setup time is maximized.

Referencing Figure 1, the polarity of DRY with respect to the sample N data output transition is undetermined because of the unknown startup logic level of the clock divider that generates the DRY signal (DRY is a frequency divide-by-two of CLK). Either the rising or the falling edge of DRY will be coincident with sample N and the polarity of DRY could invert when power is cycled off/on or when the power-down pin is cycled. Data capture from the transition and not the polarity of DRY is recommended, but not required. If the synchronization of multiple ADS5474 devices is required, it might be necessary to use a form of the CLKIN signal rather than DRY to capture the data.”

Best Regards,

0 Neal Kendrick over 13 years ago in reply to KW Nam

Prodigy 10 points

You ever get this to work? We have a need to synchronize 256 high speed A/D converters, facing the same challenges as Mr. Starr.

0 Richard Prentice over 13 years ago in reply to Neal Kendrick

TI__Mastermind 29220 points

Hi,

We have not had to do this directly, but for a *few* ADCs synchronized I have seen it done. For example, there is the EVM with two interleaved ADS5474 at http://www.ti.com/tool/ads5474adx-evm and a similar EVM with four interleaved ADS54RF63 at http://www.ti.com/tool/ads54rf63-adx4. But we did not do the synchronization nor the FPGA code for dealing with the interleaving spurs - that is the intellectual property of SP Devices who owns that FPGA code. I just offer that as an existence proof, for what its worth.

I don't know about synchronizing 256 data converters in this fashion. The issue with multiple ADS5474 or ADS5463 is that the LVDS output clock is dual data rate, so that the clock (DRDY I think it is called for data ready) is low for one sample and high for the next sample. But the device does not have a reset input to reset the phase of DRDY to a known state. So one ADC might output a sample with DRDY high while the next one over has DRDY low for the same sample.

We have newer devices that do not have this limitation. For example ADS5400 has a reset input (although you may not need 1000MHz sampling rate) to reset the phases of the output clocks and the reset pulse also causes a pulse on the SYNC output. In this manner, even if the samples from all the 256 different ADCs went through different FPGAs or ASICs and different FIFOs, if the SYNC signal were latched with the sample data then the presence of the SYNC can act as a kind of time stamp. Then if all the ADCs saw the reset pulse at the same time, then the output samples will all have a SYNC output at the same time. If the reset input were made a repetitive signal that applied a reset say every 8th sample then the sample data would all have a SYNC pulse on every 8th sample for every ADC and the sample data could all be lined up again that way. Just a suggestion. (A repetitive Reset input does not disrupt the sample data and clocking if the reset pulse were on an even boundary so that it 'reset' the DDR bus to a phase that it would have been anyway, so then the Reset input relly becomes a Sync input.)

The other approach mentioned above of discarding the DRDY signal altogether and generating a clock delayed from the sample clock to go with the sample data would get pretty tough for many many channels, I think, and at the full 400Msps rate the device-to-device min-to-max variance in prop delay may be too big for the data valid period of the sample data anyway.

Regards,

Richard P.

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ADS5474 Timing