DAC7512: SPI Timing Spec Questions

futoshi kawarazaki

Part Number: DAC7512

Tool/software:

When the Write operation is not being executed, SCLK is kept at a HIGH level.
Please refer to the red line in the figure.
In this case, are there any timing specifications for the falling edge of SYNC?
Since there is no rising edge of SCLK, I don't think t4 (SYNC to SCLK Rising Edge Setup Time) is relevant.

4 months ago

0 Paul_Frost 4 months ago

TI__Guru 53333 points

Hi Futoshi-san,

If SCLK = HIGH only, then SYNC and DIN will have no effect on the device.

0 futoshi kawarazaki 4 months ago in reply to Paul_Frost

Prodigy 115 points

Hi Paul

The write operation starts with SCLK being HIGH.

First, set SYNC to LOW.

DB15 is captured on the first Falling Edge of SCLK.

In this case, there is no SCLK rising edge to capture SYNC = LOW.

In this case, are there any timing specifications for the falling edge of SYNC?

+1 Katlynne Jones 4 months ago in reply to futoshi kawarazaki

TI__Mastermind 31488 points

Hi Futoshi-san,

T4 (SYNC to SCLK Rising Edge Setup Time) is 0ns anyway. This is to indicate that there is no requirement to have a rising edge after the SYNC falling edge.

The first SCLK falling edge should occur at least T2 (SCLK HIGH TIME) after SYNC falling edge.

Best,

Katlynne Jones

0 futoshi kawarazaki 4 months ago in reply to Katlynne Jones

Prodigy 115 points

Hi Katlynne,

I appreciate your assistance in resolving the problems.

Thank you.

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DAC7512: SPI Timing Spec Questions