Other Parts Discussed in Thread: TX7332,
Tool/software:
Dear Texas Instruments
I have been working on the design of an FPGA project for Specialist Condition Monitoring, for which the proof-of-concept design was originally done by Texas Instruments. I have a few questions I would like to be addressed by the technical team that was responsible for generating the image which is used to configure the Cypress FX3 device firmware used in the project. Please note that I will be asking very specific and technical questions related to the problem and that only the individuals responsible for the firmware programming of the Cypress FX3 device will be able to answer appropriately or else documentation stating what was configured on the firmware.
As we only have the programming image and not the source code, we were unable to determine the configuration settings used in the firmware and thus the intended behaviour of the device. So, I would like to ask about the Cypress FX3 device firmware that was configured for this project. The synchronous slave FIFO configuration was used and the only connected peripheral is the USB 3.0, I assume this is the standard configuration that you supply with the Cypress device. Please see the questions below:
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What is the buffer size of the DMA channel used in the device (this will of course refer to the DMA socket connected to the USB 3.0 on address [A0:A1] = "00".
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What configuration settings were used for flags A and B? Were they 'full flags', indicating only the availability of the DMA (DMA_READY) OR was one of the flags used as a 'partial flag' to indicate how many more 32-bit words could be written to the buffer (DMA_WATERMARK)? If not one of these configurations, please explain IN DETAIL exactly what was done in the reply.
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If 'full flags' were used, which I doubt since no counting mechanism was found to be programmed on the FPGA to this effect, then please explain how this was possibly implemented along with the answer to question 1.
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If a 'full flag' and 'partial flag' was used, as I suspect, then along with the answer to question 1, please provide the 'watermark' value used to determine when the partial flag is meant to be triggered.
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Please also state other configurations used for the flags: active high/low, low/high at startup setting used, 'dedicated thread' or 'current thread' used?
These answers are important for us to fully understand the behaviour of the device and the associated timing.
Associated Texas hardware/software used (if relevant): The board Is the SBOA361, Highly Integrated Signal Chain Solutions TX7332 and AFE5832LP for Smart Ultrasound Probes. We are using the High Speed Data Converter Pro Software. GUI Version V 5.045, DLL version 0.1, Firmware Version 0.1 and AFE5832LPTX, EVM Version 0.1.19.
Thank you in advance for your cooperation.
