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Original question:

DAC39J84: K-symbols from TI IP are not recognized by DAC

DAC39J84: Link Configuration errors in DAC3XJ8X GUI

Ryan Carpenter
Prodigy 80 points
Part Number: DAC39J84
Other Parts Discussed in Thread: DAC39J82

Tool/software:

Hello TI support,

In the DAC3XJ8X GUI we see Link Configuration errors. 

Our current FW scheme is the following:

We are using two of the TI JESD204 cores, one for each ADC (4 RX lanes per ADC) and we use 4 TX lanes from each IP core for the full 8 lanes required for our DAC.

Currently, our ADC works well and the GBTs from the FPGA side and the ADC/DAC side are all locking successfully, but we always have "Link Configuration Errors".

 

Is it possible to run the DAC using two separate TI IP cores? Right now it is set to LMFS=8411, K=32.

Do we need to just be using a single core for the DAC?

Thanks,

Ryan

  • 0
    TI__Mastermind 20755 points

    Hi Ryan,

    You can use the DAC as a single link or two separate links. This DAC supports up to 4 links but some of the functions only show supporting 2 links. Most cases, I see customers using a single link for all DUCs.

    Thanks, Chase

  • +1 in reply to Chase W
    Prodigy 80 points

    Hello Chase,

    Thanks for your response. It is still not clear to us from the documentation for the DAC39J84 how to configure two links.

     If we have HW configuration like picture above, we have a total of 8 Lanes. But we have 4 lanes from one TI JESD Ip core and 4 Lanes on the 2nd TI JESD Ip core. Both cores are configured to work with "4-2-1-1" mode. This means, that on the ILAS INIT phase both JESD TI IP cores will send the DAC information that it is configured for LMFS 4-2-1-1. But the DAC is configured for the LMFS 8-4-1-1 mode. And it looks like on the ILAS phase that the DAC acts like something like "My configuration is 8-4-1-1, but transmitter in ILAS phase sent me "4-2-1-1". Error." It fixes the Link configuration Error and stops. So, we disabled the ILAS phase in the DAC (by setting "TX does not support ILAS"). And now, we see data on the DAC outs that look correct (maybe we need to swap some LANES). This state is ok.

    But for TWO links, how can we enable it the right way? I think we have to set LMFS "4-2-1-1" mode in DAC (this will cause the ILAS phase to be correct: transmitter sends "4-2-1-1" and the DAC is also tuned for "4-2-1-1"). Do we need to enable\disable "dual mode" in the DAC? LMFS "4-2-1-1" mode is for two channels, but I am thinking we do not need to enable the "Dual mode" in DAC. Are we correct right? Next - we need to setup which LANES will be for link0 and which LANES will be for link1. Correct? Also, we are thinking that in the TI JESD IP cores we have to setup different BIDs for the ILAS phase. 

    Also, do we need to setup the same BIDs in the DAC for link0 and link1 (same as in the JESD TI IP cores for link0 and link1) or not? It is not clear from dac39j84 documentation. Can you please explain how to start two links with the configuration in the picture above? (one dac39j84, 4 LANES to one TI JESD IP Core and 4 LANES to the other one JESD IP core). 

    Thanks,

    Ryan

  • +1 in reply to Ryan Carpenter
    TI__Mastermind 20755 points

    Hi Ryan,

    Yes, this is expected behavior. If the TX doesn't support ILAS then the DAC can simply mask the link configuration error as you have found. The bank id (bid) can be set to 0 and 1 for link 0 and link 1. The lane id should be specific to each link (both links have lid between 0-3). 

    The DAC should stay in 8411 mode. This way when 4 of the 8 lanes are on link1, each link sees 4211. You do not want to enable the dual dac mode as this will set DUC C and D into powered down state and the quad DAC39J84 will act as the dual DAC39J82.

    Since JESD spec doesn't specify this ILAS information stage to be correct, we typically recommend for the link configuration error to be ignored. Once you know the system is able to get past CGS and ILAS phase, it is advised to enable the no_lane_sync bit to mask the errors from link configuration, 0x4F[bit 5], which is what I recommend to do anyways since this information from ILAS doesn't impact the DAC functionality at all other than providing the link configuration errors.

    Thanks, Chase