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ADS8686S: external resistor matching and error canceling of them

Part Number: ADS8686S
Other Parts Discussed in Thread: OPA192

Tool/software:

Hello,

I am still struggling with Vbias an leakage currents...

The datasheet mentions: 

I would interpret the linked post like the following principle:

As example:

  • Selected Range: +/- 5V
  • => Vbias = 1.8V
  • Rext: both 10k

With this, the "cancellation of any additional offset error contributed by the external resistor" can occur, if the AnalogInputVoltage is 3.6V (2xVbias) because then the introduced voltage drop via the Rext is the same.
When the external voltage differs, there has to be an offset error which will even be much more worse, when negative input voltages are measured.

Maybe you can clarify this...

Regards
Sebastian

  • Hi Sebastian,

    What do you mean by 'when the external voltage differs'?  Are you going by your model or have you been working with the ADS8686S directly?  

  • Hello Tom,

    sorry for the late answer. 

    With "external voltage" I meant the "AnalogInputVoltage" (mentioned in the LTspice screenshot).

    I am theoretically on the model (no Hardware by now).
    We are going to use the ADS8686S, besides other, for passive (voltage divider) internal supply feedback measurement.
    So we are thinking on the impact of the divider impedance.

    A colleague of mine has in the mean time the opinion, that the external resistors cancel additional offset errors, but introduce a significant gain error.
    That error would be dependent of the ratio between external and internal (1Meg) resistances...

    I hope you can understand my problem better now.

  • Hi Sebastian,

    No worries on being late!  I see what you are talking about now.  Gain can be calibrated out, or you could consider a buffer ahead of the ADC input similar to what we have incorporated on the ADS8686SEVM-PDK.  Channel BIN1 (top left corner of page 31) uses an optional OPA192 with a resistive divider input.

  • Thank you for your answer.

    So my colleague is right, that not low impedant signal source leads to a gain error...
    As the error is dependent of the relation of external to internal impedance, it also varies with the 15% tolerance of the internal impedance.
    Is this correct?

    A calibration is not possible in my system, as I want to measure static supply voltages (passive with resistive divider) which I cannot adjust to calibration points.

    With this context, I think, the following marked sentence in the datasheet is misleading, 

    and this one is wrong (it mentions cancellation of any additional gain error contributed by the external series resistance)

    In this example, the 3k external resistors introduce a 0,3% gain error but no additional offset error.

    Regards Sebastian

  • Hi Sebastian,

    Let me look into this reference design a little for you, I'm curious to see what the outcome is without using the OPAs and INAs:

    TIDA-01576 — High accuracy analog input module reference design with 16-bit 1-MSPS dual simultaneous-sampling ADC