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DAC5688 configuration problem

ASIM
Intellectual 270 points
Other Parts Discussed in Thread: DAC5688

Dear Friends,

I am trying to initialize DAC5688.

Clock2 input is 50.0Mhz

Interpolation value i have selected is 8

My desired IF is 21.4MHz

I have configured DAC5688 for interleaved data on Input-A.

value of PLL_M is 16 and PLL_N is 2

my FDAC should be 400MHZ  and i can observe 100.0MHZ on Clock1.

i expect the output to be 21.4MHz at DAC_A OUT but i dont see only a DC level.

I would request forum members to please see my code below and suggest me if i am doing anything wrong.

Following is my code to initialize DAC5688

//------------------------------------------------------------------------------
// Function: initDAC5688()
// Inputs:
// instruction byte as char instrByte
// char data byte as char byte
// Returns:
// Value read as char
// Description:
// The function initializes DAC5688
//------------------------------------------------------------------------------

void initDAC5688(void)
{
   char value;
    // CONFIG1 Register
    value = 0x00
    | (1<<6)    //insel_mode[1:0]; Farrukh.. Select A input for both channels
    | (0<<5)    //unused
    | (0<<4)    //synchr_clkin
    | (1<<3)    //twos; Farrukh.. 1=>twos complement
    | (0<<2)    //inv_inclk; Farrukh.. 0=>no inversion
    | (3<<0);   //interp_value[1:0]; Farrukh.. 3=>X8 interpolation
    dac5688_write (CONFIG1, value);
   
    // CONFIG2 Register
    value = 0x00
    | (0<<7)    //diffclk_ena; Farrukh.. 0=>single ended clock
    | (0<<6)    //clk1_in_ena
    | (0<<5)    //clk1c_ in_ena; Farrukh.. 0=>Pin acts as PLL_LOCK status
    | (0<<4)    //clko_SE_hold
    | (0<<3)    //fir4_ ena
    | (0<<2)    //qmc_ offset_ena
    | (0<<1)    //qmc_ corr_ena
    | (1<<0);   //mixer_ena   
    dac5688_write (CONFIG2, value);   

    // CONFIG3 Register
    value = 0x00
    | (0<<6)    //diffclk_dly(1:0)
    | (0<<4)    //clko_dly(1:0)
    | (0<<0);   //Reserved(3:0)   
    dac5688_write (CONFIG3, value);

    // CONFIG4 Register
    value = 0x00
    | (1<<7)    //ser_dac_ data_ena; Farrukh.. this can be set to test DAC from SPI
    | (0<<5)    //output_delay(1:0)
    | (0<<4)    //B_equals_A
    | (0<<3)    //A_equals_B
    | (0<<2)    //unused
    | (0<<1)    //reva
    | (0<<0);   //revb   
    dac5688_write (CONFIG4, value);   

    // CONFIG5 Register; Farrukh.. Leave at DEFAULT
    value = 0x00
    | (1<<7)    //sif4
    | (0<<6)    //sif_ sync_sig
    | (0<<5)    //clkdiv_sync_ena
    | (0<<4)    //clkdiv_sync_sel
    | (0<<3)    //Reserved
    | (0<<2)    //clkdiv_shift
    | (1<<1)    //mixer_gain
    | (0<<0);   //unused
    dac5688_write (CONFIG5, value);
   
   
    // CONFIG6 Register; Farrukh.. Leave at DEFAULT
    value = 0x00;  // phaseoffset(7:0)
    dac5688_write (CONFIG6, value);
   
    // CONFIG7 Register; Farrukh.. Leave at DEFAULT
    value = 0x00;  // phaseoffset(15:8)
    dac5688_write (CONFIG7, value);

    // CONFIG8 Register
    value = 0x0e;  // phaseadd(7:0)
    dac5688_write (CONFIG8, value);

    // CONFIG9 Register
    value = 0x2d;  // phaseadd(15:8)
    dac5688_write (CONFIG9, value);

    // CONFIG10 Register
    value = 0xb2;  // phaseadd(23:16)
    dac5688_write (CONFIG10, value);

    // CONFIG11 Register
    value = 0x0d;  // phaseadd(31:24)
    dac5688_write (CONFIG11, value);

    // CONFIG12 Register
    value = 0x00;  // qmc_gaina(7:0)
    dac5688_write (CONFIG12, value);
   
    // CONFIG13 Register
    value = 0x00;  // qmc_gainb(7:0)
    dac5688_write (CONFIG13, value);
   
    // CONFIG14 Register
    value = 0x00;  // qmc_phase(7:0)
    dac5688_write (CONFIG14, value);
   
   
    // CONFIG15 Register
    value = 0x00
    | (0<<6)    //qmc_phase(9:8)
    | (4<<3)    //qmc_gaina(10:8)   
    | (4<<0);   //qmc_gainb(10:8)
    dac5688_write (CONFIG15, value);

    // CONFIG16 Register
    value = 0x00;  // qmc_offseta(7:0)
    dac5688_write (CONFIG16, value);

    // CONFIG17 Register
    value = 0x00;  // qmc_offsetb(7:0)
    dac5688_write (CONFIG17, value);
   
    // CONFIG18 Register
    value = 0x00   
    | (0<<3)    //qmc_offseta(12:8)
    | (0<<2)    //unused
    | (0<<1)    //unused
    | (0<<0);   //unused       
    dac5688_write (CONFIG18, value);
   
    // CONFIG19 Register
    value = 0x00   
    | (0<<3)    //qmc_offsetb(12:8)
    | (0<<2)    //unused
    | (0<<1)    //unused
    | (0<<0);   //unused       
    dac5688_write (CONFIG19, value);

    // CONFIG20 Register
    value = 0x00;  // ser_dac_data(7:0)
    dac5688_write (CONFIG20, value);

    // CONFIG21 Register
    value = 0x00;  // ser_dac_data(15:8)
    dac5688_write (CONFIG21, value);

    // CONFIG22 Register
    value = 0x00
    | (0<<6)    //nco_sel(1:0)
    | (0<<4)    //nco_reg_sel(1:0)
    | (1<<2)    //qmcorr_reg_sel(1:0)
    | (1<<0);   //qmoffset_reg_sel(1:0)
    dac5688_write (CONFIG22, value);

    // CONFIG23 Register
    value = 0x00
    | (0<<7)    //unused
    | (0<<6)    //unused
    | (0<<3)    //fifo_sel(2:0)
    | (0<<2)    //aflag_ sel
    | (0<<1)    //unused
    | (1<<0);   //unused
    dac5688_write (CONFIG23, value);   


    // CONFIG24 Register
    value = 0x00
    | (0<<4)    //fifo_sync_strt(3:0)
    | (0<<3)    //unused
    | (0<<2)    //unused
    | (0<<1)    //unused
    | (0<<0);   //unused
    dac5688_write (CONFIG24, value);
   
   // CONFIG25 Register is all unused
  
    // CONFIG26 Register
    value = 0x00
    | (0<<7)    //io_1p8_3p3
    | (0<<6)    //unused
    | (0<<5)    //sleepb
    | (0<<4)    //sleepa
    | (1<<3)    //isbiaslpfb_a
    | (1<<2)    //isbiaslpf_b
    | (0<<1)    //PLL_ sleep
    | (1<<0);   //PLL_ena
    dac5688_write (CONFIG26, value);
   
    // CONFIG27 Register
    value = 0x00
    | (15<<3)    //coarse_daca(3:0)
    | (15<<0);   //coarse_dacb(3:0)
    dac5688_write (CONFIG27, value);   
  
   // CONFIG28 Register is Reserved
  
    // CONFIG29 Register
    value = 0x00
    | (15<<3)    //PLL_m(4:0)    // 7 means m is 8
    | (1<<0);   //PLL_n(2:0)    // 1 means n is 2
    dac5688_write (CONFIG29, value);
   
    // CONFIG30 Register
    value = 0x00
    | (0<<7)    //PLL_LPF_ reset
    | (0<<6)    //VCO_div2
    | (0<<4)    //PLL_gain(1:0)
    | (2<<0);   //PLL_range(3:0)
    dac5688_write (CONFIG30, value);
}

  • 0
    Intellectual 270 points

    Dear Friends,

    I am also unable to drive the dac5688 in mixer bypass mode. This DAC is giving me quite a tough time.

    I am driving DA[15:0] input by a free running counter updating at 50.0mhz where and i have cleared the mixer_ena  bit in config2 register.

    my dac still outputs 50.00 Mhz clock which has around 300mV amplitude on IOUTA1. Although i was expecting a ramp at the output IOUTA1.

    IOUTA1 is pulled up with a 100ohm resistor. When i read back status register it reads 0x81 which suggest my PLL is locked. The clock output i get on clk1 is 50.0MHZ.

    Can someone suggest how can i by pass mixer and directly drive my DAC output from my dac DA[15:0] input?

    Here is the function that i am using to initialize dac5688 in mixer bypass mode:

    //------------------------------------------------------------------------------
    // Function: initDAC5688_mixer_bypass( )
    // Inputs:
    // instruction byte as char instrByte
    // char data byte as char byte
    // Returns:
    // Value read as char
    // Description:
    // The function initializes DAC5688 in mixer bypass mode.
    //------------------------------------------------------------------------------
    void initDAC5688_mixer_bypass(void)
    {
       char value;
        // CONFIG1 Register
        value = 0x00
        | (1<<6)    //insel_mode[1:0];  Select A input for both channels
        | (0<<5)    //unused
        | (0<<4)    //synchr_clkin
        | (1<<3)    //twos;  1=>twos complement
        | (0<<2)    //inv_inclk;  0=>no inversion
        | (3<<0);   //interp_value[1:0]; . 3=>X8 interpolation
        dac5688_write (CONFIG1, value);
       
        // CONFIG2 Register
        value = 0x00
        | (0<<7)    //diffclk_ena;  0=>single ended clock
        | (0<<6)    //clk1_in_ena
        | (0<<5)    //clk1c_ in_ena;  0=>Pin acts as PLL_LOCK status
        | (0<<4)    //clko_SE_hold
        | (0<<3)    //fir4_ ena
        | (0<<2)    //qmc_ offset_ena
        | (0<<1)    //qmc_ corr_ena
        | (0<<0);   //mixer_ena   
        dac5688_write (CONFIG2, value);   

        // CONFIG3 Register
        value = 0x00
        | (0<<6)    //diffclk_dly(1:0)
        | (0<<4)    //clko_dly(1:0)
        | (0<<0);   //Reserved(3:0)   
        dac5688_write (CONFIG3, value);

        // CONFIG4 Register
        value = 0x00
        | (1<<7)    //ser_dac_ data_ena;  this can be set to test DAC from SPI
        | (0<<5)    //output_delay(1:0)
        | (0<<4)    //B_equals_A
        | (0<<3)    //A_equals_B
        | (0<<2)    //unused
        | (0<<1)    //reva
        | (0<<0);   //revb   
        dac5688_write (CONFIG4, value);   

        // CONFIG5 Register;  Leave at DEFAULT
        value = 0x00
        | (1<<7)    //sif4
        | (0<<6)    //sif_ sync_sig
        | (1<<5)    //clkdiv_sync_ena
        | (0<<4)    //clkdiv_sync_sel
        | (0<<3)    //Reserved
        | (0<<2)    //clkdiv_shift
        | (1<<1)    //mixer_gain
        | (0<<0);   //unused
        dac5688_write (CONFIG5, value);
       
       
        // CONFIG6 Register;  Leave at DEFAULT
        value = 0x00;  // phaseoffset(7:0)
        dac5688_write (CONFIG6, value);
       
        // CONFIG7 Register;  Leave at DEFAULT
        value = 0x00;  // phaseoffset(15:8)
        dac5688_write (CONFIG7, value);

        // CONFIG8 Register
        value = 0x0e;  // phaseadd(7:0)
        dac5688_write (CONFIG8, value);

        // CONFIG9 Register
        value = 0x00;  // phaseadd(15:8)
        dac5688_write (CONFIG9, value);

        // CONFIG10 Register
        value = 0x00;  // phaseadd(23:16)
        dac5688_write (CONFIG10, value);

        // CONFIG11 Register
        value = 0x00;  // phaseadd(31:24)
        dac5688_write (CONFIG11, value);

        // CONFIG12 Register
        value = 0x00;  // qmc_gaina(7:0)
        dac5688_write (CONFIG12, value);
       
        // CONFIG13 Register
        value = 0x00;  // qmc_gainb(7:0)
        dac5688_write (CONFIG13, value);
       
        // CONFIG14 Register
        value = 0x00;  // qmc_phase(7:0)
        dac5688_write (CONFIG14, value);
       
       
        // CONFIG15 Register
        value = 0x00
        | (0<<6)    //qmc_phase(9:8)
        | (4<<3)    //qmc_gaina(10:8)   
        | (4<<0);   //qmc_gainb(10:8)
        dac5688_write (CONFIG15, value);

        // CONFIG16 Register
        value = 0x00;  // qmc_offseta(7:0)
        dac5688_write (CONFIG16, value);

        // CONFIG17 Register
        value = 0x00;  // qmc_offsetb(7:0)
        dac5688_write (CONFIG17, value);
       
        // CONFIG18 Register
        value = 0x00   
        | (0<<3)    //qmc_offseta(12:8)
        | (0<<2)    //unused
        | (0<<1)    //unused
        | (0<<0);   //unused       
        dac5688_write (CONFIG18, value);
       
        // CONFIG19 Register
        value = 0x00   
        | (0<<3)    //qmc_offsetb(12:8)
        | (0<<2)    //unused
        | (0<<1)    //unused
        | (0<<0);   //unused       
        dac5688_write (CONFIG19, value);

        // CONFIG20 Register
        value = 0x00;  // ser_dac_data(7:0)
        dac5688_write (CONFIG20, value);

        // CONFIG21 Register
        value = 0x00;  // ser_dac_data(15:8)
        dac5688_write (CONFIG21, value);

        // CONFIG22 Register
        value = 0x00
        | (0<<6)    //nco_sel(1:0)
        | (0<<4)    //nco_reg_sel(1:0)
        | (1<<2)    //qmcorr_reg_sel(1:0)
        | (1<<0);   //qmoffset_reg_sel(1:0)
        dac5688_write (CONFIG22, value);

        // CONFIG23 Register
        value = 0x00
        | (0<<7)    //unused
        | (0<<6)    //unused
        | (0<<3)    //fifo_sel(2:0)
        | (0<<2)    //aflag_ sel
        | (0<<1)    //unused
        | (1<<0);   //unused
        dac5688_write (CONFIG23, value);   


        // CONFIG24 Register
        value = 0x00
        | (0<<4)    //fifo_sync_strt(3:0)
        | (0<<3)    //unused
        | (0<<2)    //unused
        | (0<<1)    //unused
        | (0<<0);   //unused
        dac5688_write (CONFIG24, value);
       
       // CONFIG25 Register is all unused
      
        // CONFIG26 Register
        value = 0x00
        | (0<<7)    //io_1p8_3p3
        | (0<<6)    //unused
        | (0<<5)    //sleepb
        | (0<<4)    //sleepa
        | (1<<3)    //isbiaslpfb_a
        | (1<<2)    //isbiaslpf_b
        | (0<<1)    //PLL_ sleep
        | (1<<0);   //PLL_ena
        dac5688_write (CONFIG26, value);
       
        // CONFIG27 Register
        value = 0x00
        | (15<<3)    //coarse_daca(3:0)
        | (15<<0);   //coarse_dacb(3:0)
        dac5688_write (CONFIG27, value);   
      
       // CONFIG28 Register is Reserved
      
        // CONFIG29 Register
        value = 0x00
        | (7<<3)    //PLL_m(4:0)    // 7 means m is 8
        | (1<<0);   //PLL_n(2:0)    // 1 means n is 2
        dac5688_write (CONFIG29, value);
       
        // CONFIG30 Register
        value = 0x00
        | (0<<7)    //PLL_LPF_ reset
        | (0<<6)    //VCO_div2
        | (0<<4)    //PLL_gain(1:0)
        | (0<<0);   //PLL_range(3:0)
        dac5688_write (CONFIG30, value);
    }


    Can i find configuration example codes written in C or any programming language for DAC5688? It'd be very useful for the people trying to use this chip.

    Regards,

    Asim

  • 0 in reply to ASIM
    Intellectual 270 points

    i request forum members to please reply to my post. i am anxiously waiting for reply.

    regards,

    Asim

  • 0 in reply to ASIM
    Intellectual 270 points

    Dear Friends,

    I am now able to run dac5688 in mixer bypass mode:

    following are my inputs to DAC5688:

    CLK2 = 50.000MHZ

    CLK1 (output) = 50MHZ

    TXENABLE = stays at logic 1

    SYCN = Stays at logic 1

    status register read after configuration is = 0x81

    DA[15:0] = free running counter is updating at 50MHZ clock (@ CLK1 output)

    value for M : 7 (means value of 8)

    value for N : 1 (means value of 2)

    following is my code that initializes the DAC5688 in Mixer Bypass mode:

    void initDAC5688_mixer_bypass(void)
    {
       char value;
        // CONFIG1 Register
        value = 0x00
        | (1<<6)    //insel_mode[1:0]; Farrukh.. Select A input for both channels
        | (0<<5)    //unused
        | (0<<4)    //synchr_clkin
        | (1<<3)    //twos; Farrukh.. 1=>twos complement
        | (0<<2)    //inv_inclk; Farrukh.. 0=>no inversion
        | (3<<0);   //interp_value[1:0]; Farrukh.. 3=>X8 interpolation
        dac5688_write (CONFIG1, value);
       
        // CONFIG2 Register
        value = 0x00
        | (0<<7)    //diffclk_ena; Farrukh.. 0=>single ended clock
        | (0<<6)    //clk1_in_ena
        | (0<<5)    //clk1c_ in_ena; Farrukh.. 0=>Pin acts as PLL_LOCK status
        | (0<<4)    //clko_SE_hold
        | (0<<3)    //fir4_ ena
        | (0<<2)    //qmc_ offset_ena
        | (0<<1)    //qmc_ corr_ena
        | (0<<0);   //mixer_ena   
        dac5688_write (CONFIG2, value);   

        // CONFIG3 Register
        value = 0x00
        | (0<<6)    //diffclk_dly(1:0)
        | (0<<4)    //clko_dly(1:0)
        | (0<<0);   //Reserved(3:0)   
        dac5688_write (CONFIG3, value);

        // CONFIG4 Register
        value = 0x00
        | (0<<7)    //ser_dac_ data_ena; Farrukh.. this can be set to test DAC from SPI
        | (0<<5)    //output_delay(1:0)
        | (0<<4)    //B_equals_A
        | (0<<3)    //A_equals_B
        | (0<<2)    //unused
        | (0<<1)    //reva
        | (0<<0);   //revb   
        dac5688_write (CONFIG4, value);   

        // CONFIG5 Register; Farrukh.. Leave at DEFAULT
        value = 0x00
        | (1<<7)    //sif4
        | (0<<6)    //sif_ sync_sig
        | (1<<5)    //clkdiv_sync_ena
        | (0<<4)    //clkdiv_sync_sel
        | (0<<3)    //Reserved
        | (0<<2)    //clkdiv_shift
        | (1<<1)    //mixer_gain
        | (0<<0);   //unused
        dac5688_write (CONFIG5, value);
       
       
        // CONFIG6 Register; Farrukh.. Leave at DEFAULT
        value = 0x00;  // phaseoffset(7:0)
        dac5688_write (CONFIG6, value);
       
        // CONFIG7 Register; Farrukh.. Leave at DEFAULT
        value = 0x00;  // phaseoffset(15:8)
        dac5688_write (CONFIG7, value);

        // CONFIG8 Register
        value = 0x0e;  // phaseadd(7:0)
        dac5688_write (CONFIG8, value);

        // CONFIG9 Register
        value = 0x00;  // phaseadd(15:8)
        dac5688_write (CONFIG9, value);

        // CONFIG10 Register
        value = 0x00;  // phaseadd(23:16)
        dac5688_write (CONFIG10, value);

        // CONFIG11 Register
        value = 0x00;  // phaseadd(31:24)
        dac5688_write (CONFIG11, value);

        // CONFIG12 Register
        value = 0x00;  // qmc_gaina(7:0)
        dac5688_write (CONFIG12, value);
       
        // CONFIG13 Register
        value = 0x00;  // qmc_gainb(7:0)
        dac5688_write (CONFIG13, value);
       
        // CONFIG14 Register
        value = 0x00;  // qmc_phase(7:0)
        dac5688_write (CONFIG14, value);
       
       
        // CONFIG15 Register
        value = 0x00
        | (0<<6)    //qmc_phase(9:8)
        | (4<<3)    //qmc_gaina(10:8)   
        | (4<<0);   //qmc_gainb(10:8)
        dac5688_write (CONFIG15, value);

        // CONFIG16 Register
        value = 0x00;  // qmc_offseta(7:0)
        dac5688_write (CONFIG16, value);

        // CONFIG17 Register
        value = 0x00;  // qmc_offsetb(7:0)
        dac5688_write (CONFIG17, value);
       
        // CONFIG18 Register
        value = 0x00   
        | (0<<3)    //qmc_offseta(12:8)
        | (0<<2)    //unused
        | (0<<1)    //unused
        | (0<<0);   //unused       
        dac5688_write (CONFIG18, value);
       
        // CONFIG19 Register
        value = 0x00   
        | (0<<3)    //qmc_offsetb(12:8)
        | (0<<2)    //unused
        | (0<<1)    //unused
        | (0<<0);   //unused       
        dac5688_write (CONFIG19, value);

        // CONFIG20 Register
        value = 0x00;  // ser_dac_data(7:0)
        dac5688_write (CONFIG20, value);

        // CONFIG21 Register
        value = 0x00;  // ser_dac_data(15:8)
        dac5688_write (CONFIG21, value);

        // CONFIG22 Register
        value = 0x00
        | (0<<6)    //nco_sel(1:0)
        | (0<<4)    //nco_reg_sel(1:0)
        | (1<<2)    //qmcorr_reg_sel(1:0)
        | (1<<0);   //qmoffset_reg_sel(1:0)
        dac5688_write (CONFIG22, value);

        // CONFIG23 Register
        value = 0x00
        | (0<<7)    //unused
        | (0<<6)    //unused
        | (0<<3)    //fifo_sel(2:0)
        | (0<<2)    //aflag_ sel
        | (0<<1)    //unused
        | (1<<0);   //unused
        dac5688_write (CONFIG23, value);   


        // CONFIG24 Register
        value = 0x00
        | (0<<4)    //fifo_sync_strt(3:0)
        | (0<<3)    //unused
        | (0<<2)    //unused
        | (0<<1)    //unused
        | (0<<0);   //unused
        dac5688_write (CONFIG24, value);
       
       // CONFIG25 Register is all unused
      
        // CONFIG26 Register
        value = 0x00
        | (0<<7)    //io_1p8_3p3
        | (0<<6)    //unused
        | (0<<5)    //sleepb
        | (0<<4)    //sleepa
        | (1<<3)    //isbiaslpfb_a
        | (1<<2)    //isbiaslpf_b
        | (0<<1)    //PLL_ sleep
        | (1<<0);   //PLL_ena
        dac5688_write (CONFIG26, value);
       
        // CONFIG27 Register
        value = 0x00
        | (15<<3)    //coarse_daca(3:0)
        | (15<<0);   //coarse_dacb(3:0)
        dac5688_write (CONFIG27, value);   
      
       // CONFIG28 Register is Reserved
      
        // CONFIG29 Register
        value = 0x00
        | (7<<3)    //PLL_m(4:0)    // 7 means m is 8
        | (1<<0);   //PLL_n(2:0)    // 1 means n is 2
        dac5688_write (CONFIG29, value);
       
        // CONFIG30 Register
        value = 0x00
        | (0<<7)    //PLL_LPF_ reset
        | (0<<6)    //VCO_div2
        | (0<<4)    //PLL_gain(1:0)
        | (0<<0);   //PLL_range(3:0)
        dac5688_write (CONFIG30, value);
    }

     

    but i am still unable to run my DAC5688 to generate IF. I hope some one can suggest me what inputs should i give to dac5688 and values should i write to dac5688 to make it generate IF.

    Regards,

    Asim

  • 0 in reply to ASIM
    TI__Guru* 78844 points

    ASIM,

    I have some suggestions regarding your setup:

    1. Since you are using interleaved input data format, the CLK1 frequency will need to be at 100MHz for 8x interpolation. This will create 50MSPS for the A channel and 50MSPS for the B channel.

    2. I was not sure about your setup for a free running counter at the DA[15:0]. You will need to make sure the data is formatted correctly for the interleaved mode. You mentioned that you are not able to generate IF. What will be the IF in the case?

    3. For interleaved bus mode, there must be a signal to indicate the start of bus A. You have set TXENABLE as the indicator, yet the TXENABLE signal is a constant "1".

    4. you can always use the serial DAC data and the NCO to create a IF and test your setup. See attached .txt for register configuration. You may need to sync the NCO accordingly (see config22). 

  • 0 in reply to Kang Hsia
    Intellectual 270 points

    Hi Kang,

    to begin with something easy I am trying the serial DAC data and the NCO to create IF. I had loaded the registers with the txt file you sent but the pll was unable to lock with those settings. I have modified the settings for 21.4MHz and have incremented the PLL range so that now register config31 holds 0x01. After doing this change i had following observations:

    Input clock (CLK2): 50MHZ

    Interpolation value i have selected is 8

    My desired IF is 21.4MHz

     

    value of PLL_M is 7 (x8) and PLL_N is 0 (/1)

    i can observe 100.0MHZ on Clock1.

    I am sending a counter value in the serial dac register. my TXENABLE still stays at logic 1.

    i expect the output to be a ramp modulated at 21.4MHz at DAC_A OUT but i see a ramp which has 100Mhz signal overriding it.

    I am still unable to produce IF.

    Please answer my question:

    1. In serial DAC mode do i need to provide txenable sync?

    2. Can we send TXENABLE  rising edge with every sample of the DAC channel A input? in this case the txenable will appear to be a continuous clock? is this right?

    Attached please find configuration file for my serial dac configuration.

    Regards,

    Fullscreen 3326.serdac_lock.txt Download 
    Texas Instruments Inc.
DAC5688 EVM Register Configuration

DAC5688 Registers
Address	Data
00		00
01		4B
02		01
03		00
04		80
05		92
06		00
07		00
08		0A
09		2D
0A		B2
0B		0D
0C		00
0D		00
0E		24
0F		00
10		00
11		00
12		00
13		00
14		00
15		80
16		AA
17		10
18		80
19		00
1A		0D
1B		FF
1C		00
1D		38
1E		01

CDCM7005 Registers
Address	Data
00		005FF1F0
01		02AA82DD
02		D00000A2
03		00000027
    Asim

     

  • 0 in reply to Kang Hsia
    Intellectual 270 points

    Hi Kang,

    I am confused with the various sync options available in this DAC5688 chip. Is there any application note or explanation document on various synchronization modes available in this chip. Does the TXENABLE pin only needs to be toggeled once to synchronize? or can we toggle it multiple times, continuously with every DA interleaved sample?

    Best Regards,

    Asim

     

  • 0 in reply to ASIM
    Intellectual 270 points

    Could someone please tell me how can i know if the NCO is running in my DAC5688?

    and please suggest who else can i contact for the support i need for this DAC5688 device?

     

     

     

  • 0 in reply to ASIM
    TI__Guru* 78844 points

    Hello ASIM,

    I suspect the NCO was not being synced correctly. This may be the reason why you see a ramp that has 100MHz signal overriding it.

    In you register setup, you have the NCO sync accumulator and register loading options (config16) pointed to the SIF SYNC (or SPI software sync). The NCO needs the sync signal to correctly load the counter with the counting value and to restart the counting from zero correctly. For the SIF SYNC option, you will simply need to toggle the sif_sync_sig bit in register config5. This will create a sync pulse to synchronize the NCO. 

    The reason why you will need to sync the NCO is to ensure the NCO frequency does not change as you are writing to the NCO phase registers (config6 to config11). As you are loading these phase registers, it the NCO changes frequency with every register write, there could be some random frequency occur at the output. This may be not desirable. 

    In answer to your question:

    1. To enable the serial DAC data, you do not need a sync signal. However, you will need the SIF SYNC to sync the NCO. The TXENABLE needs to be HIGH in order to enable the output. You can see the power up sequence section of the datasheet for more detail.

    2. The "Interleaved Bus Mode" in the datasheet mentioned about the TXENABLE signal requirement. If you set the "aflag_sel" to 1, then you will need a single rising edge TXENABLE Pulse to register sample A. If you are using DB15, then it can be a continuous signal.

    The various sync options is really to provide flexiblity to the user. The user may choose SIF SYNC if they do not want to connect extra logic IO ports to the DAC. They can also use TXENABLE or SYNC CMOS input to provide sync signal for multi-dac synchronization. It is up to the user to decide and follow the datasheet's instruction for implementation.

    Lastly, while your PLL VCO may lock correctly with the current setting, there are two PLL VCO settings that were tested over temperature to ensure the correct PLL lock. You may refer to page 8 of the datasheet for the recommended PLL settings. 

    For instance, you can use setting(1) or setting(2) for your PLL frequency of 400MHz. Simply set 0x1E register to 0x11 or 12 and you should be good to go. 

    -KH

  • 0 in reply to Kang Hsia
    Intellectual 270 points

    Dear Kang,

    By reading your reply i am now able to command DAC5688's NCO to generate my desired IF. for this test i had following setting:

    nco_reg_sel = 10 (config22)

    and i set sif_sync_sig bit in config5 to 1 and then 0 to apply changes to dac5688 nco phaseadd.

    Thank you so much for your help.

    Best Regards,

    Asim